arm64

Imports

Imports #

"cmd/internal/obj"
"fmt"
"strconv"
"cmd/internal/obj"
"cmd/internal/obj"
"cmd/internal/objabi"
"cmd/internal/src"
"cmd/internal/sys"
"internal/abi"
"internal/buildcfg"
"log"
"math"
"cmd/internal/obj"
"cmd/internal/obj"
"cmd/internal/objabi"
"encoding/binary"
"fmt"
"log"
"math"
"slices"
"strings"

Constants & Variables

AADC const #

const AADC = *ast.BinaryExpr

AADCS const #

const AADCS

AADCSW const #

const AADCSW

AADCW const #

const AADCW

AADD const #

const AADD

AADDS const #

const AADDS

AADDSW const #

const AADDSW

AADDW const #

const AADDW

AADR const #

const AADR

AADRP const #

const AADRP

AAESD const #

const AAESD

AAESE const #

const AAESE

AAESIMC const #

const AAESIMC

AAESMC const #

const AAESMC

AAND const #

const AAND

AANDS const #

const AANDS

AANDSW const #

const AANDSW

AANDW const #

const AANDW

AASR const #

const AASR

AASRW const #

const AASRW

AAT const #

const AAT

AB const #

const AB = obj.AJMP

ABCC const #

const ABCC

ABCS const #

const ABCS

ABEQ const #

const ABEQ

ABFI const #

const ABFI

ABFIW const #

const ABFIW

ABFM const #

const ABFM

ABFMW const #

const ABFMW

ABFXIL const #

const ABFXIL

ABFXILW const #

const ABFXILW

ABGE const #

const ABGE

ABGT const #

const ABGT

ABHI const #

const ABHI

ABHS const #

const ABHS

ABIC const #

const ABIC

ABICS const #

const ABICS

ABICSW const #

const ABICSW

ABICW const #

const ABICW

ABL const #

const ABL = obj.ACALL

ABLE const #

const ABLE

ABLO const #

const ABLO

ABLS const #

const ABLS

ABLT const #

const ABLT

ABMI const #

const ABMI

ABNE const #

const ABNE

ABPL const #

const ABPL

ABRK const #

const ABRK

ABVC const #

const ABVC

ABVS const #

const ABVS

ACASAD const #

const ACASAD

ACASALB const #

const ACASALB

ACASALD const #

const ACASALD

ACASALH const #

const ACASALH

ACASALW const #

const ACASALW

ACASAW const #

const ACASAW

ACASB const #

const ACASB

ACASD const #

const ACASD

ACASH const #

const ACASH

ACASLD const #

const ACASLD

ACASLW const #

const ACASLW

ACASPD const #

const ACASPD

ACASPW const #

const ACASPW

ACASW const #

const ACASW

ACBNZ const #

const ACBNZ

ACBNZW const #

const ACBNZW

ACBZ const #

const ACBZ

ACBZW const #

const ACBZW

ACCMN const #

const ACCMN

ACCMNW const #

const ACCMNW

ACCMP const #

const ACCMP

ACCMPW const #

const ACCMPW

ACINC const #

const ACINC

ACINCW const #

const ACINCW

ACINV const #

const ACINV

ACINVW const #

const ACINVW

ACLREX const #

const ACLREX

ACLS const #

const ACLS

ACLSW const #

const ACLSW

ACLZ const #

const ACLZ

ACLZW const #

const ACLZW

ACMN const #

const ACMN

ACMNW const #

const ACMNW

ACMP const #

const ACMP

ACMPW const #

const ACMPW

ACNEG const #

const ACNEG

ACNEGW const #

const ACNEGW

ACRC32B const #

const ACRC32B

ACRC32CB const #

const ACRC32CB

ACRC32CH const #

const ACRC32CH

ACRC32CW const #

const ACRC32CW

ACRC32CX const #

const ACRC32CX

ACRC32H const #

const ACRC32H

ACRC32W const #

const ACRC32W

ACRC32X const #

const ACRC32X

ACSEL const #

const ACSEL

ACSELW const #

const ACSELW

ACSET const #

const ACSET

ACSETM const #

const ACSETM

ACSETMW const #

const ACSETMW

ACSETW const #

const ACSETW

ACSINC const #

const ACSINC

ACSINCW const #

const ACSINCW

ACSINV const #

const ACSINV

ACSINVW const #

const ACSINVW

ACSNEG const #

const ACSNEG

ACSNEGW const #

const ACSNEGW

ADC const #

const ADC

ADCPS1 const #

const ADCPS1

ADCPS2 const #

const ADCPS2

ADCPS3 const #

const ADCPS3

ADMB const #

const ADMB

ADRPS const #

const ADRPS

ADSB const #

const ADSB

ADWORD const #

const ADWORD

AEON const #

const AEON

AEONW const #

const AEONW

AEOR const #

const AEOR

AEORW const #

const AEORW

AERET const #

const AERET

AEXTR const #

const AEXTR

AEXTRW const #

const AEXTRW

AFABSD const #

const AFABSD

AFABSS const #

const AFABSS

AFADDD const #

const AFADDD

AFADDS const #

const AFADDS

AFCCMPD const #

const AFCCMPD

AFCCMPED const #

const AFCCMPED

AFCCMPES const #

const AFCCMPES

AFCCMPS const #

const AFCCMPS

AFCMPD const #

const AFCMPD

AFCMPED const #

const AFCMPED

AFCMPES const #

const AFCMPES

AFCMPS const #

const AFCMPS

AFCSELD const #

const AFCSELD

AFCSELS const #

const AFCSELS

AFCVTDH const #

const AFCVTDH

AFCVTDS const #

const AFCVTDS

AFCVTHD const #

const AFCVTHD

AFCVTHS const #

const AFCVTHS

AFCVTSD const #

const AFCVTSD

AFCVTSH const #

const AFCVTSH

AFCVTZSD const #

const AFCVTZSD

AFCVTZSDW const #

const AFCVTZSDW

AFCVTZSS const #

const AFCVTZSS

AFCVTZSSW const #

const AFCVTZSSW

AFCVTZUD const #

const AFCVTZUD

AFCVTZUDW const #

const AFCVTZUDW

AFCVTZUS const #

const AFCVTZUS

AFCVTZUSW const #

const AFCVTZUSW

AFDIVD const #

const AFDIVD

AFDIVS const #

const AFDIVS

AFLDPD const #

const AFLDPD

AFLDPQ const #

const AFLDPQ

AFLDPS const #

const AFLDPS

AFMADDD const #

const AFMADDD

AFMADDS const #

const AFMADDS

AFMAXD const #

const AFMAXD

AFMAXNMD const #

const AFMAXNMD

AFMAXNMS const #

const AFMAXNMS

AFMAXS const #

const AFMAXS

AFMIND const #

const AFMIND

AFMINNMD const #

const AFMINNMD

AFMINNMS const #

const AFMINNMS

AFMINS const #

const AFMINS

AFMOVD const #

const AFMOVD

AFMOVQ const #

const AFMOVQ

AFMOVS const #

const AFMOVS

AFMSUBD const #

const AFMSUBD

AFMSUBS const #

const AFMSUBS

AFMULD const #

const AFMULD

AFMULS const #

const AFMULS

AFNEGD const #

const AFNEGD

AFNEGS const #

const AFNEGS

AFNMADDD const #

const AFNMADDD

AFNMADDS const #

const AFNMADDS

AFNMSUBD const #

const AFNMSUBD

AFNMSUBS const #

const AFNMSUBS

AFNMULD const #

const AFNMULD

AFNMULS const #

const AFNMULS

AFRINTAD const #

const AFRINTAD

AFRINTAS const #

const AFRINTAS

AFRINTID const #

const AFRINTID

AFRINTIS const #

const AFRINTIS

AFRINTMD const #

const AFRINTMD

AFRINTMS const #

const AFRINTMS

AFRINTND const #

const AFRINTND

AFRINTNS const #

const AFRINTNS

AFRINTPD const #

const AFRINTPD

AFRINTPS const #

const AFRINTPS

AFRINTXD const #

const AFRINTXD

AFRINTXS const #

const AFRINTXS

AFRINTZD const #

const AFRINTZD

AFRINTZS const #

const AFRINTZS

AFSQRTD const #

const AFSQRTD

AFSQRTS const #

const AFSQRTS

AFSTPD const #

const AFSTPD

AFSTPQ const #

const AFSTPQ

AFSTPS const #

const AFSTPS

AFSUBD const #

const AFSUBD

AFSUBS const #

const AFSUBS

AHINT const #

const AHINT

AHLT const #

const AHLT

AHVC const #

const AHVC

AIC const #

const AIC

AISB const #

const AISB

ALAST const #

const ALAST

ALDADDAB const #

const ALDADDAB

ALDADDAD const #

const ALDADDAD

ALDADDAH const #

const ALDADDAH

ALDADDALB const #

const ALDADDALB

ALDADDALD const #

const ALDADDALD

ALDADDALH const #

const ALDADDALH

ALDADDALW const #

const ALDADDALW

ALDADDAW const #

const ALDADDAW

ALDADDB const #

const ALDADDB

ALDADDD const #

const ALDADDD

ALDADDH const #

const ALDADDH

ALDADDLB const #

const ALDADDLB

ALDADDLD const #

const ALDADDLD

ALDADDLH const #

const ALDADDLH

ALDADDLW const #

const ALDADDLW

ALDADDW const #

const ALDADDW

ALDAR const #

const ALDAR

ALDARB const #

const ALDARB

ALDARH const #

const ALDARH

ALDARW const #

const ALDARW

ALDAXP const #

const ALDAXP

ALDAXPW const #

const ALDAXPW

ALDAXR const #

const ALDAXR

ALDAXRB const #

const ALDAXRB

ALDAXRH const #

const ALDAXRH

ALDAXRW const #

const ALDAXRW

ALDCLRAB const #

const ALDCLRAB

ALDCLRAD const #

const ALDCLRAD

ALDCLRAH const #

const ALDCLRAH

ALDCLRALB const #

const ALDCLRALB

ALDCLRALD const #

const ALDCLRALD

ALDCLRALH const #

const ALDCLRALH

ALDCLRALW const #

const ALDCLRALW

ALDCLRAW const #

const ALDCLRAW

ALDCLRB const #

const ALDCLRB

ALDCLRD const #

const ALDCLRD

ALDCLRH const #

const ALDCLRH

ALDCLRLB const #

const ALDCLRLB

ALDCLRLD const #

const ALDCLRLD

ALDCLRLH const #

const ALDCLRLH

ALDCLRLW const #

const ALDCLRLW

ALDCLRW const #

const ALDCLRW

ALDEORAB const #

const ALDEORAB

ALDEORAD const #

const ALDEORAD

ALDEORAH const #

const ALDEORAH

ALDEORALB const #

const ALDEORALB

ALDEORALD const #

const ALDEORALD

ALDEORALH const #

const ALDEORALH

ALDEORALW const #

const ALDEORALW

ALDEORAW const #

const ALDEORAW

ALDEORB const #

const ALDEORB

ALDEORD const #

const ALDEORD

ALDEORH const #

const ALDEORH

ALDEORLB const #

const ALDEORLB

ALDEORLD const #

const ALDEORLD

ALDEORLH const #

const ALDEORLH

ALDEORLW const #

const ALDEORLW

ALDEORW const #

const ALDEORW

ALDORAB const #

const ALDORAB

ALDORAD const #

const ALDORAD

ALDORAH const #

const ALDORAH

ALDORALB const #

const ALDORALB

ALDORALD const #

const ALDORALD

ALDORALH const #

const ALDORALH

ALDORALW const #

const ALDORALW

ALDORAW const #

const ALDORAW

ALDORB const #

const ALDORB

ALDORD const #

const ALDORD

ALDORH const #

const ALDORH

ALDORLB const #

const ALDORLB

ALDORLD const #

const ALDORLD

ALDORLH const #

const ALDORLH

ALDORLW const #

const ALDORLW

ALDORW const #

const ALDORW

ALDP const #

const ALDP

ALDPSW const #

const ALDPSW

ALDPW const #

const ALDPW

ALDXP const #

const ALDXP

ALDXPW const #

const ALDXPW

ALDXR const #

const ALDXR

ALDXRB const #

const ALDXRB

ALDXRH const #

const ALDXRH

ALDXRW const #

const ALDXRW

ALSL const #

const ALSL

ALSLW const #

const ALSLW

ALSR const #

const ALSR

ALSRW const #

const ALSRW

AMADD const #

const AMADD

AMADDW const #

const AMADDW

AMNEG const #

const AMNEG

AMNEGW const #

const AMNEGW

AMOVB const #

const AMOVB

AMOVBU const #

const AMOVBU

AMOVD const #

const AMOVD

AMOVH const #

const AMOVH

AMOVHU const #

const AMOVHU

AMOVK const #

const AMOVK

AMOVKW const #

const AMOVKW

AMOVN const #

const AMOVN

AMOVNW const #

const AMOVNW

AMOVP const #

const AMOVP

AMOVPD const #

const AMOVPD

AMOVPQ const #

const AMOVPQ

AMOVPS const #

const AMOVPS

AMOVPSW const #

const AMOVPSW

AMOVPW const #

const AMOVPW

AMOVW const #

const AMOVW

AMOVWU const #

const AMOVWU

AMOVZ const #

const AMOVZ

AMOVZW const #

const AMOVZW

AMRS const #

const AMRS

AMSR const #

const AMSR

AMSUB const #

const AMSUB

AMSUBW const #

const AMSUBW

AMUL const #

const AMUL

AMULW const #

const AMULW

AMVN const #

const AMVN

AMVNW const #

const AMVNW

ANEG const #

const ANEG

ANEGS const #

const ANEGS

ANEGSW const #

const ANEGSW

ANEGW const #

const ANEGW

ANGC const #

const ANGC

ANGCS const #

const ANGCS

ANGCSW const #

const ANGCSW

ANGCW const #

const ANGCW

ANOOP const #

const ANOOP

AORN const #

const AORN

AORNW const #

const AORNW

AORR const #

const AORR

AORRW const #

const AORRW

APRFM const #

const APRFM

APRFUM const #

const APRFUM

ARBIT const #

const ARBIT

ARBITW const #

const ARBITW

AREM const #

const AREM

AREMW const #

const AREMW

AREV const #

const AREV

AREV16 const #

const AREV16

AREV16W const #

const AREV16W

AREV32 const #

const AREV32

AREVW const #

const AREVW

ARM64DWARFRegisters var #

http://infocenter.arm.com/help/topic/com.arm.doc.ecm0665627/abi_sve_aadwarf_100985_0000_00_en.pdf

var ARM64DWARFRegisters = map[int16]int16{...}

ARNG_16B const #

Arrangement for ARM64 SIMD instructions

const ARNG_16B

ARNG_1D const #

Arrangement for ARM64 SIMD instructions

const ARNG_1D

ARNG_1Q const #

Arrangement for ARM64 SIMD instructions

const ARNG_1Q

ARNG_2D const #

Arrangement for ARM64 SIMD instructions

const ARNG_2D

ARNG_2S const #

Arrangement for ARM64 SIMD instructions

const ARNG_2S

ARNG_4H const #

Arrangement for ARM64 SIMD instructions

const ARNG_4H

ARNG_4S const #

Arrangement for ARM64 SIMD instructions

const ARNG_4S

ARNG_8B const #

arrangement types

const ARNG_8B = iota

ARNG_8H const #

Arrangement for ARM64 SIMD instructions

const ARNG_8H

ARNG_B const #

Arrangement for ARM64 SIMD instructions

const ARNG_B

ARNG_D const #

Arrangement for ARM64 SIMD instructions

const ARNG_D

ARNG_H const #

Arrangement for ARM64 SIMD instructions

const ARNG_H

ARNG_S const #

Arrangement for ARM64 SIMD instructions

const ARNG_S

AROR const #

const AROR

ARORW const #

const ARORW

ASBC const #

const ASBC

ASBCS const #

const ASBCS

ASBCSW const #

const ASBCSW

ASBCW const #

const ASBCW

ASBFIZ const #

const ASBFIZ

ASBFIZW const #

const ASBFIZW

ASBFM const #

const ASBFM

ASBFMW const #

const ASBFMW

ASBFX const #

const ASBFX

ASBFXW const #

const ASBFXW

ASCVTFD const #

const ASCVTFD

ASCVTFS const #

const ASCVTFS

ASCVTFWD const #

const ASCVTFWD

ASCVTFWS const #

const ASCVTFWS

ASDIV const #

const ASDIV

ASDIVW const #

const ASDIVW

ASEV const #

const ASEV

ASEVL const #

const ASEVL

ASHA1C const #

const ASHA1C

ASHA1H const #

const ASHA1H

ASHA1M const #

const ASHA1M

ASHA1P const #

const ASHA1P

ASHA1SU0 const #

const ASHA1SU0

ASHA1SU1 const #

const ASHA1SU1

ASHA256H const #

const ASHA256H

ASHA256H2 const #

const ASHA256H2

ASHA256SU0 const #

const ASHA256SU0

ASHA256SU1 const #

const ASHA256SU1

ASHA512H const #

const ASHA512H

ASHA512H2 const #

const ASHA512H2

ASHA512SU0 const #

const ASHA512SU0

ASHA512SU1 const #

const ASHA512SU1

ASMADDL const #

const ASMADDL

ASMC const #

const ASMC

ASMNEGL const #

const ASMNEGL

ASMSUBL const #

const ASMSUBL

ASMULH const #

const ASMULH

ASMULL const #

const ASMULL

ASTLR const #

const ASTLR

ASTLRB const #

const ASTLRB

ASTLRH const #

const ASTLRH

ASTLRW const #

const ASTLRW

ASTLXP const #

const ASTLXP

ASTLXPW const #

const ASTLXPW

ASTLXR const #

const ASTLXR

ASTLXRB const #

const ASTLXRB

ASTLXRH const #

const ASTLXRH

ASTLXRW const #

const ASTLXRW

ASTP const #

const ASTP

ASTPW const #

const ASTPW

ASTXP const #

const ASTXP

ASTXPW const #

const ASTXPW

ASTXR const #

const ASTXR

ASTXRB const #

const ASTXRB

ASTXRH const #

const ASTXRH

ASTXRW const #

const ASTXRW

ASUB const #

const ASUB

ASUBS const #

const ASUBS

ASUBSW const #

const ASUBSW

ASUBW const #

const ASUBW

ASVC const #

const ASVC

ASWPAB const #

const ASWPAB

ASWPAD const #

const ASWPAD

ASWPAH const #

const ASWPAH

ASWPALB const #

const ASWPALB

ASWPALD const #

const ASWPALD

ASWPALH const #

const ASWPALH

ASWPALW const #

const ASWPALW

ASWPAW const #

const ASWPAW

ASWPB const #

const ASWPB

ASWPD const #

const ASWPD

ASWPH const #

const ASWPH

ASWPLB const #

const ASWPLB

ASWPLD const #

const ASWPLD

ASWPLH const #

const ASWPLH

ASWPLW const #

const ASWPLW

ASWPW const #

const ASWPW

ASXTB const #

const ASXTB

ASXTBW const #

const ASXTBW

ASXTH const #

const ASXTH

ASXTHW const #

const ASXTHW

ASXTW const #

const ASXTW

ASYS const #

const ASYS

ASYSL const #

const ASYSL

ATBNZ const #

const ATBNZ

ATBZ const #

const ATBZ

ATLBI const #

const ATLBI

ATST const #

const ATST

ATSTW const #

const ATSTW

AUBFIZ const #

const AUBFIZ

AUBFIZW const #

const AUBFIZW

AUBFM const #

const AUBFM

AUBFMW const #

const AUBFMW

AUBFX const #

const AUBFX

AUBFXW const #

const AUBFXW

AUCVTFD const #

const AUCVTFD

AUCVTFS const #

const AUCVTFS

AUCVTFWD const #

const AUCVTFWD

AUCVTFWS const #

const AUCVTFWS

AUDIV const #

const AUDIV

AUDIVW const #

const AUDIVW

AUMADDL const #

const AUMADDL

AUMNEGL const #

const AUMNEGL

AUMSUBL const #

const AUMSUBL

AUMULH const #

const AUMULH

AUMULL const #

const AUMULL

AUREM const #

const AUREM

AUREMW const #

const AUREMW

AUXTB const #

const AUXTB

AUXTBW const #

const AUXTBW

AUXTH const #

const AUXTH

AUXTHW const #

const AUXTHW

AUXTW const #

const AUXTW

AVADD const #

const AVADD

AVADDP const #

const AVADDP

AVADDV const #

const AVADDV

AVAND const #

const AVAND

AVBCAX const #

const AVBCAX

AVBIF const #

const AVBIF

AVBIT const #

const AVBIT

AVBSL const #

const AVBSL

AVCMEQ const #

const AVCMEQ

AVCMTST const #

const AVCMTST

AVCNT const #

const AVCNT

AVDUP const #

const AVDUP

AVEOR const #

const AVEOR

AVEOR3 const #

const AVEOR3

AVEXT const #

const AVEXT

AVFMLA const #

const AVFMLA

AVFMLS const #

const AVFMLS

AVLD1 const #

const AVLD1

AVLD1R const #

const AVLD1R

AVLD2 const #

const AVLD2

AVLD2R const #

const AVLD2R

AVLD3 const #

const AVLD3

AVLD3R const #

const AVLD3R

AVLD4 const #

const AVLD4

AVLD4R const #

const AVLD4R

AVMOV const #

const AVMOV

AVMOVD const #

const AVMOVD

AVMOVI const #

const AVMOVI

AVMOVQ const #

const AVMOVQ

AVMOVS const #

const AVMOVS

AVORR const #

const AVORR

AVPMULL const #

const AVPMULL

AVPMULL2 const #

const AVPMULL2

AVRAX1 const #

const AVRAX1

AVRBIT const #

const AVRBIT

AVREV16 const #

const AVREV16

AVREV32 const #

const AVREV32

AVREV64 const #

const AVREV64

AVSHL const #

const AVSHL

AVSLI const #

const AVSLI

AVSRI const #

const AVSRI

AVST1 const #

const AVST1

AVST2 const #

const AVST2

AVST3 const #

const AVST3

AVST4 const #

const AVST4

AVSUB const #

const AVSUB

AVTBL const #

const AVTBL

AVTBX const #

const AVTBX

AVTRN1 const #

const AVTRN1

AVTRN2 const #

const AVTRN2

AVUADDLV const #

const AVUADDLV

AVUADDW const #

const AVUADDW

AVUADDW2 const #

const AVUADDW2

AVUMAX const #

const AVUMAX

AVUMIN const #

const AVUMIN

AVUSHLL const #

const AVUSHLL

AVUSHLL2 const #

const AVUSHLL2

AVUSHR const #

const AVUSHR

AVUSRA const #

const AVUSRA

AVUXTL const #

const AVUXTL

AVUXTL2 const #

const AVUXTL2

AVUZP1 const #

const AVUZP1

AVUZP2 const #

const AVUZP2

AVXAR const #

const AVXAR

AVZIP1 const #

const AVZIP1

AVZIP2 const #

const AVZIP2

AWFE const #

const AWFE

AWFI const #

const AWFI

AWORD const #

const AWORD

AYIELD const #

const AYIELD

Anames var #

var Anames = []string{...}

BIG const #

const BIG = *ast.BinaryExpr

BRANCH const #

const BRANCH

BRANCH14BITS const #

const BRANCH14BITS

BRANCH19BITS const #

const BRANCH19BITS

C_AACON const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_AACON

C_AACON2 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_AACON2

C_ABCON const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_ABCON

C_ABCON0 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_ABCON0

C_ADDCON const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_ADDCON

C_ADDCON0 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_ADDCON0

C_ADDCON2 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_ADDCON2

C_ADDR const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_ADDR

C_AECON const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_AECON

C_AMCON const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_AMCON

C_ARNG const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_ARNG

C_BITCON const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_BITCON

C_COND const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_COND

C_ELEM const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_ELEM

C_EXTREG const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_EXTREG

C_FCON const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_FCON

C_FREG const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_FREG

C_GOK const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_GOK

C_GOTADDR const #

The GOT slot for a symbol in -dynlink mode.

const C_GOTADDR

C_LACON const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_LACON

C_LAUTO const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_LAUTO

C_LAUTOPOOL const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_LAUTOPOOL

C_LBRA const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_LBRA

C_LCON const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_LCON

C_LEXT const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_LEXT

C_LIST const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_LIST

C_LOREG const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_LOREG

C_LOREGPOOL const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_LOREGPOOL

C_MBCON const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_MBCON

C_MOVCON const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_MOVCON

C_MOVCON2 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_MOVCON2

C_MOVCON3 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_MOVCON3

C_NAUTO4K const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_NAUTO4K

C_NCLASS const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_NCLASS

C_NONE const #

optab is sorted based on the order of these constants and the first match is chosen. The more specific class needs to come earlier.

const C_NONE = *ast.BinaryExpr

C_NOREG4K const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_NOREG4K

C_NPAUTO const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_NPAUTO

C_NPAUTO_16 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_NPAUTO_16

C_NPOREG const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_NPOREG

C_NPOREG_16 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_NPOREG_16

C_NQAUTO_16 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_NQAUTO_16

C_NQOREG_16 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_NQOREG_16

C_NSAUTO const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_NSAUTO

C_NSAUTO_16 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_NSAUTO_16

C_NSAUTO_4 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_NSAUTO_4

C_NSAUTO_8 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_NSAUTO_8

C_NSOREG const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_NSOREG

C_NSOREG_16 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_NSOREG_16

C_NSOREG_4 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_NSOREG_4

C_NSOREG_8 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_NSOREG_8

C_PAIR const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_PAIR

C_PPAUTO const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_PPAUTO

C_PPAUTO_16 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_PPAUTO_16

C_PPOREG const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_PPOREG

C_PPOREG_16 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_PPOREG_16

C_PQAUTO_16 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_PQAUTO_16

C_PQOREG_16 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_PQOREG_16

C_PSAUTO const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_PSAUTO

C_PSAUTO_16 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_PSAUTO_16

C_PSAUTO_4 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_PSAUTO_4

C_PSAUTO_8 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_PSAUTO_8

C_PSOREG const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_PSOREG

C_PSOREG_16 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_PSOREG_16

C_PSOREG_4 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_PSOREG_4

C_PSOREG_8 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_PSOREG_8

C_REG const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_REG

C_ROFF const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_ROFF

C_RSP const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_RSP

C_SBRA const #

TODO(aram): only one branch class should be enough

const C_SBRA

C_SEXT1 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_SEXT1

C_SEXT16 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_SEXT16

C_SEXT2 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_SEXT2

C_SEXT4 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_SEXT4

C_SEXT8 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_SEXT8

C_SHIFT const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_SHIFT

C_SPOP const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_SPOP

C_SPR const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_SPR

C_TEXTSIZE const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_TEXTSIZE

C_TLS_IE const #

TLS "var" in initial exec mode: will become a memory address (chosen by the program linker) that the dynamic linker will fill with the offset from the thread local base.

const C_TLS_IE

C_TLS_LE const #

TLS "var" in local exec mode: will become a constant offset from thread local base that is ultimately chosen by the program linker.

const C_TLS_LE

C_UAUTO16K const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_UAUTO16K

C_UAUTO16K_16 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_UAUTO16K_16

C_UAUTO16K_8 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_UAUTO16K_8

C_UAUTO32K const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_UAUTO32K

C_UAUTO32K_16 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_UAUTO32K_16

C_UAUTO4K const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_UAUTO4K

C_UAUTO4K_16 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_UAUTO4K_16

C_UAUTO4K_2 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_UAUTO4K_2

C_UAUTO4K_4 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_UAUTO4K_4

C_UAUTO4K_8 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_UAUTO4K_8

C_UAUTO64K const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_UAUTO64K

C_UAUTO8K const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_UAUTO8K

C_UAUTO8K_16 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_UAUTO8K_16

C_UAUTO8K_4 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_UAUTO8K_4

C_UAUTO8K_8 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_UAUTO8K_8

C_UOREG16K const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_UOREG16K

C_UOREG16K_16 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_UOREG16K_16

C_UOREG16K_8 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_UOREG16K_8

C_UOREG32K const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_UOREG32K

C_UOREG32K_16 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_UOREG32K_16

C_UOREG4K const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_UOREG4K

C_UOREG4K_16 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_UOREG4K_16

C_UOREG4K_2 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_UOREG4K_2

C_UOREG4K_4 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_UOREG4K_4

C_UOREG4K_8 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_UOREG4K_8

C_UOREG64K const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_UOREG64K

C_UOREG8K const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_UOREG8K

C_UOREG8K_16 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_UOREG8K_16

C_UOREG8K_4 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_UOREG8K_4

C_UOREG8K_8 const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_UOREG8K_8

C_VCON const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_VCON

C_VCONADDR const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_VCONADDR

C_VREG const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_VREG

C_XPOST const #

const C_XPOST = *ast.BinaryExpr

C_XPRE const #

const C_XPRE = *ast.BinaryExpr

C_ZAUTO const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_ZAUTO

C_ZCON const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_ZCON

C_ZOREG const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_ZOREG

C_ZREG const #

go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64

const C_ZREG

FCMP const #

const FCMP

FLOAT const #

const FLOAT

FOLL const #

const FOLL

FREGEXT const #

Register assignments: compiler allocates R0 up as temps compiler allocates register variables R7-R25 compiler allocates external registers R26 down compiler allocates register variables F7-F26 compiler allocates external registers F26 down

const FREGEXT = REG_F26

FREGMAX const #

const FREGMAX = REG_F26

FREGMIN const #

const FREGMIN = REG_F7

FREGRET const #

const FREGRET = REG_F0

LABEL const #

mark flags

const LABEL = *ast.BinaryExpr

LEAF const #

const LEAF

LFROM const #

Optab.flag

const LFROM = *ast.BinaryExpr

LIST const #

const LIST

LOAD const #

const LOAD

LSL0_32 const #

const LSL0_32 = *ast.BinaryExpr

LSL0_64 const #

const LSL0_64 = *ast.BinaryExpr

LTO const #

const LTO

Linkarm64 var #

var Linkarm64 = obj.LinkArch{...}

NFREG const #

const NFREG = 32

NOSCHED const #

const NOSCHED

NOTUSETMP const #

const NOTUSETMP

NREG const #

const NREG = 32

NSNAME const #

const NSNAME = 8

NSYM const #

const NSYM = 50

OP_NOOP const #

Used for padding NOOP instruction

const OP_NOOP = 0xd503201f

REGCTXT const #

const REGCTXT = REG_R26

REGFP const #

const REGFP = REG_R29

REGFROM const #

const REGFROM = 1

REGG const #

const REGG = REG_R28

REGLINK const #

const REGLINK = REG_R30

REGMAX const #

const REGMAX = REG_R25

REGMIN const #

const REGMIN = REG_R7

REGPR const #

const REGPR = REG_R18

REGRT1 const #

const REGRT1 = REG_R16

REGRT2 const #

const REGRT2 = REG_R17

REGSP const #

const REGSP = REG_RSP

REGTMP const #

const REGTMP = REG_R27

REGZERO const #

ARM64 uses R31 as both stack pointer and zero register, depending on the instruction. To differentiate RSP from ZR, we use a different numeric value for REGZERO and REGSP.

const REGZERO = REG_R31

REG_ACTLR_EL1 const #

const REG_ACTLR_EL1

REG_AFSR0_EL1 const #

const REG_AFSR0_EL1

REG_AFSR1_EL1 const #

const REG_AFSR1_EL1

REG_AIDR_EL1 const #

const REG_AIDR_EL1

REG_AMAIR_EL1 const #

const REG_AMAIR_EL1

REG_AMCFGR_EL0 const #

const REG_AMCFGR_EL0

REG_AMCGCR_EL0 const #

const REG_AMCGCR_EL0

REG_AMCNTENCLR0_EL0 const #

const REG_AMCNTENCLR0_EL0

REG_AMCNTENCLR1_EL0 const #

const REG_AMCNTENCLR1_EL0

REG_AMCNTENSET0_EL0 const #

const REG_AMCNTENSET0_EL0

REG_AMCNTENSET1_EL0 const #

const REG_AMCNTENSET1_EL0

REG_AMCR_EL0 const #

const REG_AMCR_EL0

REG_AMEVCNTR00_EL0 const #

const REG_AMEVCNTR00_EL0

REG_AMEVCNTR010_EL0 const #

const REG_AMEVCNTR010_EL0

REG_AMEVCNTR011_EL0 const #

const REG_AMEVCNTR011_EL0

REG_AMEVCNTR012_EL0 const #

const REG_AMEVCNTR012_EL0

REG_AMEVCNTR013_EL0 const #

const REG_AMEVCNTR013_EL0

REG_AMEVCNTR014_EL0 const #

const REG_AMEVCNTR014_EL0

REG_AMEVCNTR015_EL0 const #

const REG_AMEVCNTR015_EL0

REG_AMEVCNTR01_EL0 const #

const REG_AMEVCNTR01_EL0

REG_AMEVCNTR02_EL0 const #

const REG_AMEVCNTR02_EL0

REG_AMEVCNTR03_EL0 const #

const REG_AMEVCNTR03_EL0

REG_AMEVCNTR04_EL0 const #

const REG_AMEVCNTR04_EL0

REG_AMEVCNTR05_EL0 const #

const REG_AMEVCNTR05_EL0

REG_AMEVCNTR06_EL0 const #

const REG_AMEVCNTR06_EL0

REG_AMEVCNTR07_EL0 const #

const REG_AMEVCNTR07_EL0

REG_AMEVCNTR08_EL0 const #

const REG_AMEVCNTR08_EL0

REG_AMEVCNTR09_EL0 const #

const REG_AMEVCNTR09_EL0

REG_AMEVCNTR10_EL0 const #

const REG_AMEVCNTR10_EL0

REG_AMEVCNTR110_EL0 const #

const REG_AMEVCNTR110_EL0

REG_AMEVCNTR111_EL0 const #

const REG_AMEVCNTR111_EL0

REG_AMEVCNTR112_EL0 const #

const REG_AMEVCNTR112_EL0

REG_AMEVCNTR113_EL0 const #

const REG_AMEVCNTR113_EL0

REG_AMEVCNTR114_EL0 const #

const REG_AMEVCNTR114_EL0

REG_AMEVCNTR115_EL0 const #

const REG_AMEVCNTR115_EL0

REG_AMEVCNTR11_EL0 const #

const REG_AMEVCNTR11_EL0

REG_AMEVCNTR12_EL0 const #

const REG_AMEVCNTR12_EL0

REG_AMEVCNTR13_EL0 const #

const REG_AMEVCNTR13_EL0

REG_AMEVCNTR14_EL0 const #

const REG_AMEVCNTR14_EL0

REG_AMEVCNTR15_EL0 const #

const REG_AMEVCNTR15_EL0

REG_AMEVCNTR16_EL0 const #

const REG_AMEVCNTR16_EL0

REG_AMEVCNTR17_EL0 const #

const REG_AMEVCNTR17_EL0

REG_AMEVCNTR18_EL0 const #

const REG_AMEVCNTR18_EL0

REG_AMEVCNTR19_EL0 const #

const REG_AMEVCNTR19_EL0

REG_AMEVTYPER00_EL0 const #

const REG_AMEVTYPER00_EL0

REG_AMEVTYPER010_EL0 const #

const REG_AMEVTYPER010_EL0

REG_AMEVTYPER011_EL0 const #

const REG_AMEVTYPER011_EL0

REG_AMEVTYPER012_EL0 const #

const REG_AMEVTYPER012_EL0

REG_AMEVTYPER013_EL0 const #

const REG_AMEVTYPER013_EL0

REG_AMEVTYPER014_EL0 const #

const REG_AMEVTYPER014_EL0

REG_AMEVTYPER015_EL0 const #

const REG_AMEVTYPER015_EL0

REG_AMEVTYPER01_EL0 const #

const REG_AMEVTYPER01_EL0

REG_AMEVTYPER02_EL0 const #

const REG_AMEVTYPER02_EL0

REG_AMEVTYPER03_EL0 const #

const REG_AMEVTYPER03_EL0

REG_AMEVTYPER04_EL0 const #

const REG_AMEVTYPER04_EL0

REG_AMEVTYPER05_EL0 const #

const REG_AMEVTYPER05_EL0

REG_AMEVTYPER06_EL0 const #

const REG_AMEVTYPER06_EL0

REG_AMEVTYPER07_EL0 const #

const REG_AMEVTYPER07_EL0

REG_AMEVTYPER08_EL0 const #

const REG_AMEVTYPER08_EL0

REG_AMEVTYPER09_EL0 const #

const REG_AMEVTYPER09_EL0

REG_AMEVTYPER10_EL0 const #

const REG_AMEVTYPER10_EL0

REG_AMEVTYPER110_EL0 const #

const REG_AMEVTYPER110_EL0

REG_AMEVTYPER111_EL0 const #

const REG_AMEVTYPER111_EL0

REG_AMEVTYPER112_EL0 const #

const REG_AMEVTYPER112_EL0

REG_AMEVTYPER113_EL0 const #

const REG_AMEVTYPER113_EL0

REG_AMEVTYPER114_EL0 const #

const REG_AMEVTYPER114_EL0

REG_AMEVTYPER115_EL0 const #

const REG_AMEVTYPER115_EL0

REG_AMEVTYPER11_EL0 const #

const REG_AMEVTYPER11_EL0

REG_AMEVTYPER12_EL0 const #

const REG_AMEVTYPER12_EL0

REG_AMEVTYPER13_EL0 const #

const REG_AMEVTYPER13_EL0

REG_AMEVTYPER14_EL0 const #

const REG_AMEVTYPER14_EL0

REG_AMEVTYPER15_EL0 const #

const REG_AMEVTYPER15_EL0

REG_AMEVTYPER16_EL0 const #

const REG_AMEVTYPER16_EL0

REG_AMEVTYPER17_EL0 const #

const REG_AMEVTYPER17_EL0

REG_AMEVTYPER18_EL0 const #

const REG_AMEVTYPER18_EL0

REG_AMEVTYPER19_EL0 const #

const REG_AMEVTYPER19_EL0

REG_AMUSERENR_EL0 const #

const REG_AMUSERENR_EL0

REG_APDAKeyHi_EL1 const #

const REG_APDAKeyHi_EL1

REG_APDAKeyLo_EL1 const #

const REG_APDAKeyLo_EL1

REG_APDBKeyHi_EL1 const #

const REG_APDBKeyHi_EL1

REG_APDBKeyLo_EL1 const #

const REG_APDBKeyLo_EL1

REG_APGAKeyHi_EL1 const #

const REG_APGAKeyHi_EL1

REG_APGAKeyLo_EL1 const #

const REG_APGAKeyLo_EL1

REG_APIAKeyHi_EL1 const #

const REG_APIAKeyHi_EL1

REG_APIAKeyLo_EL1 const #

const REG_APIAKeyLo_EL1

REG_APIBKeyHi_EL1 const #

const REG_APIBKeyHi_EL1

REG_APIBKeyLo_EL1 const #

const REG_APIBKeyLo_EL1

REG_ARNG const #

bits 0-4 indicates register: Vn bits 5-8 indicates arrangement:

const REG_ARNG = *ast.BinaryExpr

REG_CCSIDR2_EL1 const #

const REG_CCSIDR2_EL1

REG_CCSIDR_EL1 const #

const REG_CCSIDR_EL1

REG_CLIDR_EL1 const #

const REG_CLIDR_EL1

REG_CNTFRQ_EL0 const #

const REG_CNTFRQ_EL0

REG_CNTKCTL_EL1 const #

const REG_CNTKCTL_EL1

REG_CNTPCT_EL0 const #

const REG_CNTPCT_EL0

REG_CNTPS_CTL_EL1 const #

const REG_CNTPS_CTL_EL1

REG_CNTPS_CVAL_EL1 const #

const REG_CNTPS_CVAL_EL1

REG_CNTPS_TVAL_EL1 const #

const REG_CNTPS_TVAL_EL1

REG_CNTP_CTL_EL0 const #

const REG_CNTP_CTL_EL0

REG_CNTP_CVAL_EL0 const #

const REG_CNTP_CVAL_EL0

REG_CNTP_TVAL_EL0 const #

const REG_CNTP_TVAL_EL0

REG_CNTVCT_EL0 const #

const REG_CNTVCT_EL0

REG_CNTV_CTL_EL0 const #

const REG_CNTV_CTL_EL0

REG_CNTV_CVAL_EL0 const #

const REG_CNTV_CVAL_EL0

REG_CNTV_TVAL_EL0 const #

const REG_CNTV_TVAL_EL0

REG_CONTEXTIDR_EL1 const #

const REG_CONTEXTIDR_EL1

REG_CPACR_EL1 const #

const REG_CPACR_EL1

REG_CSSELR_EL1 const #

const REG_CSSELR_EL1

REG_CTR_EL0 const #

const REG_CTR_EL0

REG_CurrentEL const #

const REG_CurrentEL

REG_DAIF const #

const REG_DAIF

REG_DBGAUTHSTATUS_EL1 const #

const REG_DBGAUTHSTATUS_EL1

REG_DBGBCR0_EL1 const #

const REG_DBGBCR0_EL1

REG_DBGBCR10_EL1 const #

const REG_DBGBCR10_EL1

REG_DBGBCR11_EL1 const #

const REG_DBGBCR11_EL1

REG_DBGBCR12_EL1 const #

const REG_DBGBCR12_EL1

REG_DBGBCR13_EL1 const #

const REG_DBGBCR13_EL1

REG_DBGBCR14_EL1 const #

const REG_DBGBCR14_EL1

REG_DBGBCR15_EL1 const #

const REG_DBGBCR15_EL1

REG_DBGBCR1_EL1 const #

const REG_DBGBCR1_EL1

REG_DBGBCR2_EL1 const #

const REG_DBGBCR2_EL1

REG_DBGBCR3_EL1 const #

const REG_DBGBCR3_EL1

REG_DBGBCR4_EL1 const #

const REG_DBGBCR4_EL1

REG_DBGBCR5_EL1 const #

const REG_DBGBCR5_EL1

REG_DBGBCR6_EL1 const #

const REG_DBGBCR6_EL1

REG_DBGBCR7_EL1 const #

const REG_DBGBCR7_EL1

REG_DBGBCR8_EL1 const #

const REG_DBGBCR8_EL1

REG_DBGBCR9_EL1 const #

const REG_DBGBCR9_EL1

REG_DBGBVR0_EL1 const #

const REG_DBGBVR0_EL1

REG_DBGBVR10_EL1 const #

const REG_DBGBVR10_EL1

REG_DBGBVR11_EL1 const #

const REG_DBGBVR11_EL1

REG_DBGBVR12_EL1 const #

const REG_DBGBVR12_EL1

REG_DBGBVR13_EL1 const #

const REG_DBGBVR13_EL1

REG_DBGBVR14_EL1 const #

const REG_DBGBVR14_EL1

REG_DBGBVR15_EL1 const #

const REG_DBGBVR15_EL1

REG_DBGBVR1_EL1 const #

const REG_DBGBVR1_EL1

REG_DBGBVR2_EL1 const #

const REG_DBGBVR2_EL1

REG_DBGBVR3_EL1 const #

const REG_DBGBVR3_EL1

REG_DBGBVR4_EL1 const #

const REG_DBGBVR4_EL1

REG_DBGBVR5_EL1 const #

const REG_DBGBVR5_EL1

REG_DBGBVR6_EL1 const #

const REG_DBGBVR6_EL1

REG_DBGBVR7_EL1 const #

const REG_DBGBVR7_EL1

REG_DBGBVR8_EL1 const #

const REG_DBGBVR8_EL1

REG_DBGBVR9_EL1 const #

const REG_DBGBVR9_EL1

REG_DBGCLAIMCLR_EL1 const #

const REG_DBGCLAIMCLR_EL1

REG_DBGCLAIMSET_EL1 const #

const REG_DBGCLAIMSET_EL1

REG_DBGDTRRX_EL0 const #

const REG_DBGDTRRX_EL0

REG_DBGDTRTX_EL0 const #

const REG_DBGDTRTX_EL0

REG_DBGDTR_EL0 const #

const REG_DBGDTR_EL0

REG_DBGPRCR_EL1 const #

const REG_DBGPRCR_EL1

REG_DBGWCR0_EL1 const #

const REG_DBGWCR0_EL1

REG_DBGWCR10_EL1 const #

const REG_DBGWCR10_EL1

REG_DBGWCR11_EL1 const #

const REG_DBGWCR11_EL1

REG_DBGWCR12_EL1 const #

const REG_DBGWCR12_EL1

REG_DBGWCR13_EL1 const #

const REG_DBGWCR13_EL1

REG_DBGWCR14_EL1 const #

const REG_DBGWCR14_EL1

REG_DBGWCR15_EL1 const #

const REG_DBGWCR15_EL1

REG_DBGWCR1_EL1 const #

const REG_DBGWCR1_EL1

REG_DBGWCR2_EL1 const #

const REG_DBGWCR2_EL1

REG_DBGWCR3_EL1 const #

const REG_DBGWCR3_EL1

REG_DBGWCR4_EL1 const #

const REG_DBGWCR4_EL1

REG_DBGWCR5_EL1 const #

const REG_DBGWCR5_EL1

REG_DBGWCR6_EL1 const #

const REG_DBGWCR6_EL1

REG_DBGWCR7_EL1 const #

const REG_DBGWCR7_EL1

REG_DBGWCR8_EL1 const #

const REG_DBGWCR8_EL1

REG_DBGWCR9_EL1 const #

const REG_DBGWCR9_EL1

REG_DBGWVR0_EL1 const #

const REG_DBGWVR0_EL1

REG_DBGWVR10_EL1 const #

const REG_DBGWVR10_EL1

REG_DBGWVR11_EL1 const #

const REG_DBGWVR11_EL1

REG_DBGWVR12_EL1 const #

const REG_DBGWVR12_EL1

REG_DBGWVR13_EL1 const #

const REG_DBGWVR13_EL1

REG_DBGWVR14_EL1 const #

const REG_DBGWVR14_EL1

REG_DBGWVR15_EL1 const #

const REG_DBGWVR15_EL1

REG_DBGWVR1_EL1 const #

const REG_DBGWVR1_EL1

REG_DBGWVR2_EL1 const #

const REG_DBGWVR2_EL1

REG_DBGWVR3_EL1 const #

const REG_DBGWVR3_EL1

REG_DBGWVR4_EL1 const #

const REG_DBGWVR4_EL1

REG_DBGWVR5_EL1 const #

const REG_DBGWVR5_EL1

REG_DBGWVR6_EL1 const #

const REG_DBGWVR6_EL1

REG_DBGWVR7_EL1 const #

const REG_DBGWVR7_EL1

REG_DBGWVR8_EL1 const #

const REG_DBGWVR8_EL1

REG_DBGWVR9_EL1 const #

const REG_DBGWVR9_EL1

REG_DCZID_EL0 const #

const REG_DCZID_EL0

REG_DISR_EL1 const #

const REG_DISR_EL1

REG_DIT const #

const REG_DIT

REG_DLR_EL0 const #

const REG_DLR_EL0

REG_DSPSR_EL0 const #

const REG_DSPSR_EL0

REG_ELEM const #

bits 0-4 indicates register: Vn bits 5-8 indicates arrangement:

const REG_ELEM

REG_ELEM_END const #

bits 0-4 indicates register: Vn bits 5-8 indicates arrangement:

const REG_ELEM_END

REG_ELR_EL1 const #

const REG_ELR_EL1

REG_ERRIDR_EL1 const #

const REG_ERRIDR_EL1

REG_ERRSELR_EL1 const #

const REG_ERRSELR_EL1

REG_ERXADDR_EL1 const #

const REG_ERXADDR_EL1

REG_ERXCTLR_EL1 const #

const REG_ERXCTLR_EL1

REG_ERXFR_EL1 const #

const REG_ERXFR_EL1

REG_ERXMISC0_EL1 const #

const REG_ERXMISC0_EL1

REG_ERXMISC1_EL1 const #

const REG_ERXMISC1_EL1

REG_ERXMISC2_EL1 const #

const REG_ERXMISC2_EL1

REG_ERXMISC3_EL1 const #

const REG_ERXMISC3_EL1

REG_ERXPFGCDN_EL1 const #

const REG_ERXPFGCDN_EL1

REG_ERXPFGCTL_EL1 const #

const REG_ERXPFGCTL_EL1

REG_ERXPFGF_EL1 const #

const REG_ERXPFGF_EL1

REG_ERXSTATUS_EL1 const #

const REG_ERXSTATUS_EL1

REG_ESR_EL1 const #

const REG_ESR_EL1

REG_EXT const #

const REG_EXT = *ast.BinaryExpr

REG_F0 const #

scalar floating point

const REG_F0

REG_F1 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_F1

REG_F10 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_F10

REG_F11 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_F11

REG_F12 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_F12

REG_F13 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_F13

REG_F14 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_F14

REG_F15 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_F15

REG_F16 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_F16

REG_F17 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_F17

REG_F18 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_F18

REG_F19 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_F19

REG_F2 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_F2

REG_F20 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_F20

REG_F21 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_F21

REG_F22 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_F22

REG_F23 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_F23

REG_F24 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_F24

REG_F25 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_F25

REG_F26 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_F26

REG_F27 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_F27

REG_F28 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_F28

REG_F29 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_F29

REG_F3 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_F3

REG_F30 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_F30

REG_F31 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_F31

REG_F4 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_F4

REG_F5 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_F5

REG_F6 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_F6

REG_F7 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_F7

REG_F8 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_F8

REG_F9 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_F9

REG_FAR_EL1 const #

const REG_FAR_EL1

REG_FPCR const #

const REG_FPCR

REG_FPSR const #

const REG_FPSR

REG_GCR_EL1 const #

const REG_GCR_EL1

REG_GMID_EL1 const #

const REG_GMID_EL1

REG_ICC_AP0R0_EL1 const #

const REG_ICC_AP0R0_EL1

REG_ICC_AP0R1_EL1 const #

const REG_ICC_AP0R1_EL1

REG_ICC_AP0R2_EL1 const #

const REG_ICC_AP0R2_EL1

REG_ICC_AP0R3_EL1 const #

const REG_ICC_AP0R3_EL1

REG_ICC_AP1R0_EL1 const #

const REG_ICC_AP1R0_EL1

REG_ICC_AP1R1_EL1 const #

const REG_ICC_AP1R1_EL1

REG_ICC_AP1R2_EL1 const #

const REG_ICC_AP1R2_EL1

REG_ICC_AP1R3_EL1 const #

const REG_ICC_AP1R3_EL1

REG_ICC_ASGI1R_EL1 const #

const REG_ICC_ASGI1R_EL1

REG_ICC_BPR0_EL1 const #

const REG_ICC_BPR0_EL1

REG_ICC_BPR1_EL1 const #

const REG_ICC_BPR1_EL1

REG_ICC_CTLR_EL1 const #

const REG_ICC_CTLR_EL1

REG_ICC_DIR_EL1 const #

const REG_ICC_DIR_EL1

REG_ICC_EOIR0_EL1 const #

const REG_ICC_EOIR0_EL1

REG_ICC_EOIR1_EL1 const #

const REG_ICC_EOIR1_EL1

REG_ICC_HPPIR0_EL1 const #

const REG_ICC_HPPIR0_EL1

REG_ICC_HPPIR1_EL1 const #

const REG_ICC_HPPIR1_EL1

REG_ICC_IAR0_EL1 const #

const REG_ICC_IAR0_EL1

REG_ICC_IAR1_EL1 const #

const REG_ICC_IAR1_EL1

REG_ICC_IGRPEN0_EL1 const #

const REG_ICC_IGRPEN0_EL1

REG_ICC_IGRPEN1_EL1 const #

const REG_ICC_IGRPEN1_EL1

REG_ICC_PMR_EL1 const #

const REG_ICC_PMR_EL1

REG_ICC_RPR_EL1 const #

const REG_ICC_RPR_EL1

REG_ICC_SGI0R_EL1 const #

const REG_ICC_SGI0R_EL1

REG_ICC_SGI1R_EL1 const #

const REG_ICC_SGI1R_EL1

REG_ICC_SRE_EL1 const #

const REG_ICC_SRE_EL1

REG_ICV_AP0R0_EL1 const #

const REG_ICV_AP0R0_EL1

REG_ICV_AP0R1_EL1 const #

const REG_ICV_AP0R1_EL1

REG_ICV_AP0R2_EL1 const #

const REG_ICV_AP0R2_EL1

REG_ICV_AP0R3_EL1 const #

const REG_ICV_AP0R3_EL1

REG_ICV_AP1R0_EL1 const #

const REG_ICV_AP1R0_EL1

REG_ICV_AP1R1_EL1 const #

const REG_ICV_AP1R1_EL1

REG_ICV_AP1R2_EL1 const #

const REG_ICV_AP1R2_EL1

REG_ICV_AP1R3_EL1 const #

const REG_ICV_AP1R3_EL1

REG_ICV_BPR0_EL1 const #

const REG_ICV_BPR0_EL1

REG_ICV_BPR1_EL1 const #

const REG_ICV_BPR1_EL1

REG_ICV_CTLR_EL1 const #

const REG_ICV_CTLR_EL1

REG_ICV_DIR_EL1 const #

const REG_ICV_DIR_EL1

REG_ICV_EOIR0_EL1 const #

const REG_ICV_EOIR0_EL1

REG_ICV_EOIR1_EL1 const #

const REG_ICV_EOIR1_EL1

REG_ICV_HPPIR0_EL1 const #

const REG_ICV_HPPIR0_EL1

REG_ICV_HPPIR1_EL1 const #

const REG_ICV_HPPIR1_EL1

REG_ICV_IAR0_EL1 const #

const REG_ICV_IAR0_EL1

REG_ICV_IAR1_EL1 const #

const REG_ICV_IAR1_EL1

REG_ICV_IGRPEN0_EL1 const #

const REG_ICV_IGRPEN0_EL1

REG_ICV_IGRPEN1_EL1 const #

const REG_ICV_IGRPEN1_EL1

REG_ICV_PMR_EL1 const #

const REG_ICV_PMR_EL1

REG_ICV_RPR_EL1 const #

const REG_ICV_RPR_EL1

REG_ID_AA64AFR0_EL1 const #

const REG_ID_AA64AFR0_EL1

REG_ID_AA64AFR1_EL1 const #

const REG_ID_AA64AFR1_EL1

REG_ID_AA64DFR0_EL1 const #

const REG_ID_AA64DFR0_EL1

REG_ID_AA64DFR1_EL1 const #

const REG_ID_AA64DFR1_EL1

REG_ID_AA64ISAR0_EL1 const #

const REG_ID_AA64ISAR0_EL1

REG_ID_AA64ISAR1_EL1 const #

const REG_ID_AA64ISAR1_EL1

REG_ID_AA64MMFR0_EL1 const #

const REG_ID_AA64MMFR0_EL1

REG_ID_AA64MMFR1_EL1 const #

const REG_ID_AA64MMFR1_EL1

REG_ID_AA64MMFR2_EL1 const #

const REG_ID_AA64MMFR2_EL1

REG_ID_AA64PFR0_EL1 const #

const REG_ID_AA64PFR0_EL1

REG_ID_AA64PFR1_EL1 const #

const REG_ID_AA64PFR1_EL1

REG_ID_AA64ZFR0_EL1 const #

const REG_ID_AA64ZFR0_EL1

REG_ID_AFR0_EL1 const #

const REG_ID_AFR0_EL1

REG_ID_DFR0_EL1 const #

const REG_ID_DFR0_EL1

REG_ID_ISAR0_EL1 const #

const REG_ID_ISAR0_EL1

REG_ID_ISAR1_EL1 const #

const REG_ID_ISAR1_EL1

REG_ID_ISAR2_EL1 const #

const REG_ID_ISAR2_EL1

REG_ID_ISAR3_EL1 const #

const REG_ID_ISAR3_EL1

REG_ID_ISAR4_EL1 const #

const REG_ID_ISAR4_EL1

REG_ID_ISAR5_EL1 const #

const REG_ID_ISAR5_EL1

REG_ID_ISAR6_EL1 const #

const REG_ID_ISAR6_EL1

REG_ID_MMFR0_EL1 const #

const REG_ID_MMFR0_EL1

REG_ID_MMFR1_EL1 const #

const REG_ID_MMFR1_EL1

REG_ID_MMFR2_EL1 const #

const REG_ID_MMFR2_EL1

REG_ID_MMFR3_EL1 const #

const REG_ID_MMFR3_EL1

REG_ID_MMFR4_EL1 const #

const REG_ID_MMFR4_EL1

REG_ID_PFR0_EL1 const #

const REG_ID_PFR0_EL1

REG_ID_PFR1_EL1 const #

const REG_ID_PFR1_EL1

REG_ID_PFR2_EL1 const #

const REG_ID_PFR2_EL1

REG_ISR_EL1 const #

const REG_ISR_EL1

REG_LORC_EL1 const #

const REG_LORC_EL1

REG_LOREA_EL1 const #

const REG_LOREA_EL1

REG_LORID_EL1 const #

const REG_LORID_EL1

REG_LORN_EL1 const #

const REG_LORN_EL1

REG_LORSA_EL1 const #

const REG_LORSA_EL1

REG_LSL const #

Not registers, but flags that can be combined with regular register constants to indicate extended register conversion. When checking, you should subtract obj.RBaseARM64 first. From this difference, bit 11 indicates extended register, bits 8-10 select the conversion mode. REG_LSL is the index shift specifier, bit 9 indicates shifted offset register.

const REG_LSL = *ast.BinaryExpr

REG_MAIR_EL1 const #

const REG_MAIR_EL1

REG_MDCCINT_EL1 const #

const REG_MDCCINT_EL1

REG_MDCCSR_EL0 const #

const REG_MDCCSR_EL0

REG_MDRAR_EL1 const #

const REG_MDRAR_EL1

REG_MDSCR_EL1 const #

const REG_MDSCR_EL1

REG_MIDR_EL1 const #

const REG_MIDR_EL1

REG_MPAM0_EL1 const #

const REG_MPAM0_EL1

REG_MPAM1_EL1 const #

const REG_MPAM1_EL1

REG_MPAMIDR_EL1 const #

const REG_MPAMIDR_EL1

REG_MPIDR_EL1 const #

const REG_MPIDR_EL1

REG_MVFR0_EL1 const #

const REG_MVFR0_EL1

REG_MVFR1_EL1 const #

const REG_MVFR1_EL1

REG_MVFR2_EL1 const #

const REG_MVFR2_EL1

REG_NZCV const #

const REG_NZCV

REG_OSDLR_EL1 const #

const REG_OSDLR_EL1

REG_OSDTRRX_EL1 const #

const REG_OSDTRRX_EL1

REG_OSDTRTX_EL1 const #

const REG_OSDTRTX_EL1

REG_OSECCR_EL1 const #

const REG_OSECCR_EL1

REG_OSLAR_EL1 const #

const REG_OSLAR_EL1

REG_OSLSR_EL1 const #

const REG_OSLSR_EL1

REG_PAN const #

const REG_PAN

REG_PAR_EL1 const #

const REG_PAR_EL1

REG_PMBIDR_EL1 const #

const REG_PMBIDR_EL1

REG_PMBLIMITR_EL1 const #

const REG_PMBLIMITR_EL1

REG_PMBPTR_EL1 const #

const REG_PMBPTR_EL1

REG_PMBSR_EL1 const #

const REG_PMBSR_EL1

REG_PMCCFILTR_EL0 const #

const REG_PMCCFILTR_EL0

REG_PMCCNTR_EL0 const #

const REG_PMCCNTR_EL0

REG_PMCEID0_EL0 const #

const REG_PMCEID0_EL0

REG_PMCEID1_EL0 const #

const REG_PMCEID1_EL0

REG_PMCNTENCLR_EL0 const #

const REG_PMCNTENCLR_EL0

REG_PMCNTENSET_EL0 const #

const REG_PMCNTENSET_EL0

REG_PMCR_EL0 const #

const REG_PMCR_EL0

REG_PMEVCNTR0_EL0 const #

const REG_PMEVCNTR0_EL0

REG_PMEVCNTR10_EL0 const #

const REG_PMEVCNTR10_EL0

REG_PMEVCNTR11_EL0 const #

const REG_PMEVCNTR11_EL0

REG_PMEVCNTR12_EL0 const #

const REG_PMEVCNTR12_EL0

REG_PMEVCNTR13_EL0 const #

const REG_PMEVCNTR13_EL0

REG_PMEVCNTR14_EL0 const #

const REG_PMEVCNTR14_EL0

REG_PMEVCNTR15_EL0 const #

const REG_PMEVCNTR15_EL0

REG_PMEVCNTR16_EL0 const #

const REG_PMEVCNTR16_EL0

REG_PMEVCNTR17_EL0 const #

const REG_PMEVCNTR17_EL0

REG_PMEVCNTR18_EL0 const #

const REG_PMEVCNTR18_EL0

REG_PMEVCNTR19_EL0 const #

const REG_PMEVCNTR19_EL0

REG_PMEVCNTR1_EL0 const #

const REG_PMEVCNTR1_EL0

REG_PMEVCNTR20_EL0 const #

const REG_PMEVCNTR20_EL0

REG_PMEVCNTR21_EL0 const #

const REG_PMEVCNTR21_EL0

REG_PMEVCNTR22_EL0 const #

const REG_PMEVCNTR22_EL0

REG_PMEVCNTR23_EL0 const #

const REG_PMEVCNTR23_EL0

REG_PMEVCNTR24_EL0 const #

const REG_PMEVCNTR24_EL0

REG_PMEVCNTR25_EL0 const #

const REG_PMEVCNTR25_EL0

REG_PMEVCNTR26_EL0 const #

const REG_PMEVCNTR26_EL0

REG_PMEVCNTR27_EL0 const #

const REG_PMEVCNTR27_EL0

REG_PMEVCNTR28_EL0 const #

const REG_PMEVCNTR28_EL0

REG_PMEVCNTR29_EL0 const #

const REG_PMEVCNTR29_EL0

REG_PMEVCNTR2_EL0 const #

const REG_PMEVCNTR2_EL0

REG_PMEVCNTR30_EL0 const #

const REG_PMEVCNTR30_EL0

REG_PMEVCNTR3_EL0 const #

const REG_PMEVCNTR3_EL0

REG_PMEVCNTR4_EL0 const #

const REG_PMEVCNTR4_EL0

REG_PMEVCNTR5_EL0 const #

const REG_PMEVCNTR5_EL0

REG_PMEVCNTR6_EL0 const #

const REG_PMEVCNTR6_EL0

REG_PMEVCNTR7_EL0 const #

const REG_PMEVCNTR7_EL0

REG_PMEVCNTR8_EL0 const #

const REG_PMEVCNTR8_EL0

REG_PMEVCNTR9_EL0 const #

const REG_PMEVCNTR9_EL0

REG_PMEVTYPER0_EL0 const #

const REG_PMEVTYPER0_EL0

REG_PMEVTYPER10_EL0 const #

const REG_PMEVTYPER10_EL0

REG_PMEVTYPER11_EL0 const #

const REG_PMEVTYPER11_EL0

REG_PMEVTYPER12_EL0 const #

const REG_PMEVTYPER12_EL0

REG_PMEVTYPER13_EL0 const #

const REG_PMEVTYPER13_EL0

REG_PMEVTYPER14_EL0 const #

const REG_PMEVTYPER14_EL0

REG_PMEVTYPER15_EL0 const #

const REG_PMEVTYPER15_EL0

REG_PMEVTYPER16_EL0 const #

const REG_PMEVTYPER16_EL0

REG_PMEVTYPER17_EL0 const #

const REG_PMEVTYPER17_EL0

REG_PMEVTYPER18_EL0 const #

const REG_PMEVTYPER18_EL0

REG_PMEVTYPER19_EL0 const #

const REG_PMEVTYPER19_EL0

REG_PMEVTYPER1_EL0 const #

const REG_PMEVTYPER1_EL0

REG_PMEVTYPER20_EL0 const #

const REG_PMEVTYPER20_EL0

REG_PMEVTYPER21_EL0 const #

const REG_PMEVTYPER21_EL0

REG_PMEVTYPER22_EL0 const #

const REG_PMEVTYPER22_EL0

REG_PMEVTYPER23_EL0 const #

const REG_PMEVTYPER23_EL0

REG_PMEVTYPER24_EL0 const #

const REG_PMEVTYPER24_EL0

REG_PMEVTYPER25_EL0 const #

const REG_PMEVTYPER25_EL0

REG_PMEVTYPER26_EL0 const #

const REG_PMEVTYPER26_EL0

REG_PMEVTYPER27_EL0 const #

const REG_PMEVTYPER27_EL0

REG_PMEVTYPER28_EL0 const #

const REG_PMEVTYPER28_EL0

REG_PMEVTYPER29_EL0 const #

const REG_PMEVTYPER29_EL0

REG_PMEVTYPER2_EL0 const #

const REG_PMEVTYPER2_EL0

REG_PMEVTYPER30_EL0 const #

const REG_PMEVTYPER30_EL0

REG_PMEVTYPER3_EL0 const #

const REG_PMEVTYPER3_EL0

REG_PMEVTYPER4_EL0 const #

const REG_PMEVTYPER4_EL0

REG_PMEVTYPER5_EL0 const #

const REG_PMEVTYPER5_EL0

REG_PMEVTYPER6_EL0 const #

const REG_PMEVTYPER6_EL0

REG_PMEVTYPER7_EL0 const #

const REG_PMEVTYPER7_EL0

REG_PMEVTYPER8_EL0 const #

const REG_PMEVTYPER8_EL0

REG_PMEVTYPER9_EL0 const #

const REG_PMEVTYPER9_EL0

REG_PMINTENCLR_EL1 const #

const REG_PMINTENCLR_EL1

REG_PMINTENSET_EL1 const #

const REG_PMINTENSET_EL1

REG_PMMIR_EL1 const #

const REG_PMMIR_EL1

REG_PMOVSCLR_EL0 const #

const REG_PMOVSCLR_EL0

REG_PMOVSSET_EL0 const #

const REG_PMOVSSET_EL0

REG_PMSCR_EL1 const #

const REG_PMSCR_EL1

REG_PMSELR_EL0 const #

const REG_PMSELR_EL0

REG_PMSEVFR_EL1 const #

const REG_PMSEVFR_EL1

REG_PMSFCR_EL1 const #

const REG_PMSFCR_EL1

REG_PMSICR_EL1 const #

const REG_PMSICR_EL1

REG_PMSIDR_EL1 const #

const REG_PMSIDR_EL1

REG_PMSIRR_EL1 const #

const REG_PMSIRR_EL1

REG_PMSLATFR_EL1 const #

const REG_PMSLATFR_EL1

REG_PMSWINC_EL0 const #

const REG_PMSWINC_EL0

REG_PMUSERENR_EL0 const #

const REG_PMUSERENR_EL0

REG_PMXEVCNTR_EL0 const #

const REG_PMXEVCNTR_EL0

REG_PMXEVTYPER_EL0 const #

const REG_PMXEVTYPER_EL0

REG_R0 const #

integer

const REG_R0 = *ast.BinaryExpr

REG_R1 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_R1

REG_R10 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_R10

REG_R11 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_R11

REG_R12 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_R12

REG_R13 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_R13

REG_R14 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_R14

REG_R15 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_R15

REG_R16 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_R16

REG_R17 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_R17

REG_R18 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_R18

REG_R19 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_R19

REG_R2 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_R2

REG_R20 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_R20

REG_R21 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_R21

REG_R22 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_R22

REG_R23 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_R23

REG_R24 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_R24

REG_R25 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_R25

REG_R26 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_R26

REG_R27 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_R27

REG_R28 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_R28

REG_R29 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_R29

REG_R3 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_R3

REG_R30 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_R30

REG_R31 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_R31

REG_R4 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_R4

REG_R5 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_R5

REG_R6 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_R6

REG_R7 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_R7

REG_R8 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_R8

REG_R9 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_R9

REG_REVIDR_EL1 const #

const REG_REVIDR_EL1

REG_RGSR_EL1 const #

const REG_RGSR_EL1

REG_RMR_EL1 const #

const REG_RMR_EL1

REG_RNDR const #

const REG_RNDR

REG_RNDRRS const #

const REG_RNDRRS

REG_RSP const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_RSP = *ast.BinaryExpr

REG_RVBAR_EL1 const #

const REG_RVBAR_EL1

REG_SCTLR_EL1 const #

const REG_SCTLR_EL1

REG_SCXTNUM_EL0 const #

const REG_SCXTNUM_EL0

REG_SCXTNUM_EL1 const #

const REG_SCXTNUM_EL1

REG_SPECIAL const #

Special registers, after subtracting obj.RBaseARM64, bit 12 indicates a special register and the low bits select the register. SYSREG_END is the last item in the automatically generated system register declaration, and it is defined in the sysRegEnc.go file. Define the special register after REG_SPECIAL, the first value of it should be REG_{name} = SYSREG_END + iota.

const REG_SPECIAL = *ast.BinaryExpr

REG_SPSR_EL1 const #

const REG_SPSR_EL1

REG_SPSR_abt const #

const REG_SPSR_abt

REG_SPSR_fiq const #

const REG_SPSR_fiq

REG_SPSR_irq const #

const REG_SPSR_irq

REG_SPSR_und const #

const REG_SPSR_und

REG_SPSel const #

const REG_SPSel

REG_SP_EL0 const #

const REG_SP_EL0

REG_SP_EL1 const #

const REG_SP_EL1

REG_SSBS const #

const REG_SSBS

REG_SXTB const #

const REG_SXTB

REG_SXTH const #

const REG_SXTH

REG_SXTW const #

const REG_SXTW

REG_SXTX const #

const REG_SXTX

REG_TCO const #

const REG_TCO

REG_TCR_EL1 const #

const REG_TCR_EL1

REG_TFSRE0_EL1 const #

const REG_TFSRE0_EL1

REG_TFSR_EL1 const #

const REG_TFSR_EL1

REG_TPIDRRO_EL0 const #

const REG_TPIDRRO_EL0

REG_TPIDR_EL0 const #

const REG_TPIDR_EL0

REG_TPIDR_EL1 const #

const REG_TPIDR_EL1

REG_TRFCR_EL1 const #

const REG_TRFCR_EL1

REG_TTBR0_EL1 const #

const REG_TTBR0_EL1

REG_TTBR1_EL1 const #

const REG_TTBR1_EL1

REG_UAO const #

const REG_UAO

REG_UXTB const #

const REG_UXTB = *ast.BinaryExpr

REG_UXTH const #

const REG_UXTH

REG_UXTW const #

const REG_UXTW

REG_UXTX const #

const REG_UXTX

REG_V0 const #

SIMD

const REG_V0

REG_V1 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_V1

REG_V10 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_V10

REG_V11 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_V11

REG_V12 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_V12

REG_V13 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_V13

REG_V14 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_V14

REG_V15 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_V15

REG_V16 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_V16

REG_V17 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_V17

REG_V18 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_V18

REG_V19 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_V19

REG_V2 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_V2

REG_V20 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_V20

REG_V21 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_V21

REG_V22 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_V22

REG_V23 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_V23

REG_V24 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_V24

REG_V25 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_V25

REG_V26 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_V26

REG_V27 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_V27

REG_V28 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_V28

REG_V29 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_V29

REG_V3 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_V3

REG_V30 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_V30

REG_V31 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_V31

REG_V4 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_V4

REG_V5 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_V5

REG_V6 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_V6

REG_V7 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_V7

REG_V8 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_V8

REG_V9 const #

General purpose registers, kept in the low bits of Prog.Reg.

const REG_V9

REG_VBAR_EL1 const #

const REG_VBAR_EL1

REG_ZCR_EL1 const #

const REG_ZCR_EL1

S32 const #

const S32 = *ast.BinaryExpr

S64 const #

const S64 = *ast.BinaryExpr

SHIFT_AR const #

const SHIFT_AR = *ast.BinaryExpr

SHIFT_LL const #

shift types

const SHIFT_LL = *ast.BinaryExpr

SHIFT_LR const #

const SHIFT_LR = *ast.BinaryExpr

SHIFT_ROR const #

const SHIFT_ROR = *ast.BinaryExpr

SPOP_AL const #

const SPOP_AL

SPOP_ALLE1 const #

const SPOP_ALLE1

SPOP_ALLE1IS const #

const SPOP_ALLE1IS

SPOP_ALLE1OS const #

const SPOP_ALLE1OS

SPOP_ALLE2 const #

const SPOP_ALLE2

SPOP_ALLE2IS const #

const SPOP_ALLE2IS

SPOP_ALLE2OS const #

const SPOP_ALLE2OS

SPOP_ALLE3 const #

const SPOP_ALLE3

SPOP_ALLE3IS const #

const SPOP_ALLE3IS

SPOP_ALLE3OS const #

const SPOP_ALLE3OS

SPOP_ASIDE1 const #

const SPOP_ASIDE1

SPOP_ASIDE1IS const #

const SPOP_ASIDE1IS

SPOP_ASIDE1OS const #

const SPOP_ASIDE1OS

SPOP_BEGIN const #

const SPOP_BEGIN SpecialOperand = *ast.BinaryExpr

SPOP_CGDSW const #

const SPOP_CGDSW

SPOP_CGDVAC const #

const SPOP_CGDVAC

SPOP_CGDVADP const #

const SPOP_CGDVADP

SPOP_CGDVAP const #

const SPOP_CGDVAP

SPOP_CGSW const #

const SPOP_CGSW

SPOP_CGVAC const #

const SPOP_CGVAC

SPOP_CGVADP const #

const SPOP_CGVADP

SPOP_CGVAP const #

const SPOP_CGVAP

SPOP_CIGDSW const #

const SPOP_CIGDSW

SPOP_CIGDVAC const #

const SPOP_CIGDVAC

SPOP_CIGSW const #

const SPOP_CIGSW

SPOP_CIGVAC const #

const SPOP_CIGVAC

SPOP_CISW const #

const SPOP_CISW

SPOP_CIVAC const #

const SPOP_CIVAC

SPOP_CSW const #

const SPOP_CSW

SPOP_CVAC const #

const SPOP_CVAC

SPOP_CVADP const #

const SPOP_CVADP

SPOP_CVAP const #

const SPOP_CVAP

SPOP_CVAU const #

const SPOP_CVAU

SPOP_DAIFClr const #

const SPOP_DAIFClr

SPOP_DAIFSet const #

PSTATE fields

const SPOP_DAIFSet

SPOP_END const #

const SPOP_END

SPOP_EQ const #

Condition code, EQ, NE, etc. Their relative order to EQ is matter.

const SPOP_EQ

SPOP_GE const #

const SPOP_GE

SPOP_GT const #

const SPOP_GT

SPOP_GVA const #

const SPOP_GVA

SPOP_GZVA const #

const SPOP_GZVA

SPOP_HI const #

const SPOP_HI

SPOP_HS const #

const SPOP_HS

SPOP_IGDSW const #

const SPOP_IGDSW

SPOP_IGDVAC const #

const SPOP_IGDVAC

SPOP_IGSW const #

const SPOP_IGSW

SPOP_IGVAC const #

const SPOP_IGVAC

SPOP_IPAS2E1 const #

const SPOP_IPAS2E1

SPOP_IPAS2E1IS const #

const SPOP_IPAS2E1IS

SPOP_IPAS2E1OS const #

const SPOP_IPAS2E1OS

SPOP_IPAS2LE1 const #

const SPOP_IPAS2LE1

SPOP_IPAS2LE1IS const #

const SPOP_IPAS2LE1IS

SPOP_IPAS2LE1OS const #

const SPOP_IPAS2LE1OS

SPOP_ISW const #

const SPOP_ISW

SPOP_IVAC const #

const SPOP_IVAC

SPOP_LE const #

const SPOP_LE

SPOP_LO const #

const SPOP_LO

SPOP_LS const #

const SPOP_LS

SPOP_LT const #

const SPOP_LT

SPOP_MI const #

const SPOP_MI

SPOP_NE const #

const SPOP_NE

SPOP_NV const #

const SPOP_NV

SPOP_PL const #

const SPOP_PL

SPOP_PLDL1KEEP const #

PRFM

const SPOP_PLDL1KEEP SpecialOperand = iota

SPOP_PLDL1STRM const #

const SPOP_PLDL1STRM

SPOP_PLDL2KEEP const #

const SPOP_PLDL2KEEP

SPOP_PLDL2STRM const #

const SPOP_PLDL2STRM

SPOP_PLDL3KEEP const #

const SPOP_PLDL3KEEP

SPOP_PLDL3STRM const #

const SPOP_PLDL3STRM

SPOP_PLIL1KEEP const #

const SPOP_PLIL1KEEP

SPOP_PLIL1STRM const #

const SPOP_PLIL1STRM

SPOP_PLIL2KEEP const #

const SPOP_PLIL2KEEP

SPOP_PLIL2STRM const #

const SPOP_PLIL2STRM

SPOP_PLIL3KEEP const #

const SPOP_PLIL3KEEP

SPOP_PLIL3STRM const #

const SPOP_PLIL3STRM

SPOP_PSTL1KEEP const #

const SPOP_PSTL1KEEP

SPOP_PSTL1STRM const #

const SPOP_PSTL1STRM

SPOP_PSTL2KEEP const #

const SPOP_PSTL2KEEP

SPOP_PSTL2STRM const #

const SPOP_PSTL2STRM

SPOP_PSTL3KEEP const #

const SPOP_PSTL3KEEP

SPOP_PSTL3STRM const #

const SPOP_PSTL3STRM

SPOP_RIPAS2E1 const #

const SPOP_RIPAS2E1

SPOP_RIPAS2E1IS const #

const SPOP_RIPAS2E1IS

SPOP_RIPAS2E1OS const #

const SPOP_RIPAS2E1OS

SPOP_RIPAS2LE1 const #

const SPOP_RIPAS2LE1

SPOP_RIPAS2LE1IS const #

const SPOP_RIPAS2LE1IS

SPOP_RIPAS2LE1OS const #

const SPOP_RIPAS2LE1OS

SPOP_RVAAE1 const #

const SPOP_RVAAE1

SPOP_RVAAE1IS const #

const SPOP_RVAAE1IS

SPOP_RVAAE1OS const #

const SPOP_RVAAE1OS

SPOP_RVAALE1 const #

const SPOP_RVAALE1

SPOP_RVAALE1IS const #

const SPOP_RVAALE1IS

SPOP_RVAALE1OS const #

const SPOP_RVAALE1OS

SPOP_RVAE1 const #

const SPOP_RVAE1

SPOP_RVAE1IS const #

const SPOP_RVAE1IS

SPOP_RVAE1OS const #

const SPOP_RVAE1OS

SPOP_RVAE2 const #

const SPOP_RVAE2

SPOP_RVAE2IS const #

const SPOP_RVAE2IS

SPOP_RVAE2OS const #

const SPOP_RVAE2OS

SPOP_RVAE3 const #

const SPOP_RVAE3

SPOP_RVAE3IS const #

const SPOP_RVAE3IS

SPOP_RVAE3OS const #

const SPOP_RVAE3OS

SPOP_RVALE1 const #

const SPOP_RVALE1

SPOP_RVALE1IS const #

const SPOP_RVALE1IS

SPOP_RVALE1OS const #

const SPOP_RVALE1OS

SPOP_RVALE2 const #

const SPOP_RVALE2

SPOP_RVALE2IS const #

const SPOP_RVALE2IS

SPOP_RVALE2OS const #

const SPOP_RVALE2OS

SPOP_RVALE3 const #

const SPOP_RVALE3

SPOP_RVALE3IS const #

const SPOP_RVALE3IS

SPOP_RVALE3OS const #

const SPOP_RVALE3OS

SPOP_VAAE1 const #

const SPOP_VAAE1

SPOP_VAAE1IS const #

const SPOP_VAAE1IS

SPOP_VAAE1OS const #

const SPOP_VAAE1OS

SPOP_VAALE1 const #

const SPOP_VAALE1

SPOP_VAALE1IS const #

const SPOP_VAALE1IS

SPOP_VAALE1OS const #

const SPOP_VAALE1OS

SPOP_VAE1 const #

const SPOP_VAE1

SPOP_VAE1IS const #

const SPOP_VAE1IS

SPOP_VAE1OS const #

const SPOP_VAE1OS

SPOP_VAE2 const #

const SPOP_VAE2

SPOP_VAE2IS const #

const SPOP_VAE2IS

SPOP_VAE2OS const #

const SPOP_VAE2OS

SPOP_VAE3 const #

const SPOP_VAE3

SPOP_VAE3IS const #

const SPOP_VAE3IS

SPOP_VAE3OS const #

const SPOP_VAE3OS

SPOP_VALE1 const #

const SPOP_VALE1

SPOP_VALE1IS const #

const SPOP_VALE1IS

SPOP_VALE1OS const #

const SPOP_VALE1OS

SPOP_VALE2 const #

const SPOP_VALE2

SPOP_VALE2IS const #

const SPOP_VALE2IS

SPOP_VALE2OS const #

const SPOP_VALE2OS

SPOP_VALE3 const #

const SPOP_VALE3

SPOP_VALE3IS const #

const SPOP_VALE3IS

SPOP_VALE3OS const #

const SPOP_VALE3OS

SPOP_VC const #

const SPOP_VC

SPOP_VMALLE1 const #

const SPOP_VMALLE1

SPOP_VMALLE1IS const #

TLBI

const SPOP_VMALLE1IS

SPOP_VMALLE1OS const #

const SPOP_VMALLE1OS

SPOP_VMALLS12E1 const #

const SPOP_VMALLS12E1

SPOP_VMALLS12E1IS const #

const SPOP_VMALLS12E1IS

SPOP_VMALLS12E1OS const #

const SPOP_VMALLS12E1OS

SPOP_VS const #

const SPOP_VS

SPOP_ZVA const #

const SPOP_ZVA

SR_READ const #

const SR_READ = *ast.BinaryExpr

SR_WRITE const #

const SR_WRITE

SYNC const #

const SYNC

SYSREG_BEGIN const #

const SYSREG_BEGIN = *ast.BinaryExpr

SYSREG_END const #

const SYSREG_END

Sbit const #

const Sbit = *ast.BinaryExpr

SystemReg var #

var SystemReg = []struct{...}{...}

_SpecialOperand_index var #

var _SpecialOperand_index = [...]uint16{...}

_SpecialOperand_name const #

const _SpecialOperand_name = "PLDL1KEEPPLDL1STRMPLDL2KEEPPLDL2STRMPLDL3KEEPPLDL3STRMPLIL1KEEPPLIL1STRMPLIL2KEEPPLIL2STRMPLIL3KEEPPLIL3STRMPSTL1KEEPPSTL1STRMPSTL2KEEPPSTL2STRMPSTL3KEEPPSTL3STRMVMALLE1ISVAE1ISASIDE1ISVAAE1ISVALE1ISVAALE1ISVMALLE1VAE1ASIDE1VAAE1VALE1VAALE1IPAS2E1ISIPAS2LE1ISALLE2ISVAE2ISALLE1ISVALE2ISVMALLS12E1ISIPAS2E1IPAS2LE1ALLE2VAE2ALLE1VALE2VMALLS12E1ALLE3ISVAE3ISVALE3ISALLE3VAE3VALE3VMALLE1OSVAE1OSASIDE1OSVAAE1OSVALE1OSVAALE1OSRVAE1ISRVAAE1ISRVALE1ISRVAALE1ISRVAE1OSRVAAE1OSRVALE1OSRVAALE1OSRVAE1RVAAE1RVALE1RVAALE1RIPAS2E1ISRIPAS2LE1ISALLE2OSVAE2OSALLE1OSVALE2OSVMALLS12E1OSRVAE2ISRVALE2ISIPAS2E1OSRIPAS2E1RIPAS2E1OSIPAS2LE1OSRIPAS2LE1RIPAS2LE1OSRVAE2OSRVALE2OSRVAE2RVALE2ALLE3OSVAE3OSVALE3OSRVAE3ISRVALE3ISRVAE3OSRVALE3OSRVAE3RVALE3IVACISWCSWCISWZVACVACCVAUCIVACIGVACIGSWIGDVACIGDSWCGSWCGDSWCIGSWCIGDSWGVAGZVACGVACCGDVACCGVAPCGDVAPCGVADPCGDVADPCIGVACCIGDVACCVAPCVADPDAIFSetDAIFClrEQNEHSLOMIPLVSVCHILSGELTGTLEALNVEND"

atomicCASP var #

var atomicCASP = map[obj.As]uint32{...}

atomicLDADD var #

known field values of an instruction.

var atomicLDADD = map[obj.As]uint32{...}

atomicSWP var #

var atomicSWP = map[obj.As]uint32{...}

cnames7 var #

This order should be strictly consistent to that in a.out.go.

var cnames7 = []string{...}

funcAlign const #

const funcAlign = 16

maxPCDisp const #

Maximum PC-relative displacement. The actual limit is ±2²⁰, but we are conservative to avoid needing to recompute the literal pool flush points as span-dependent jumps are enlarged.

const maxPCDisp = *ast.BinaryExpr

oprange var #

var oprange [*ast.BinaryExpr][]Optab

optab var #

var optab = []Optab{...}

prfopfield var #

var prfopfield = map[SpecialOperand]uint32{...}

pstatefield var #

Valid pstate field values, and value to use in instruction. Doesn't include special registers.

var pstatefield = []struct{...}{...}

strcond var #

var strcond = [16]string{...}

sysInstFields var #

sysInstFields helps convert SYS alias instructions to SYS instructions. For example, the format of TLBI is: TLBI {, }. It's equivalent to: SYS #, C8, , #{, }. The field hasOperand2 indicates whether Xt is required. It helps to check some combinations that may be undefined, such as TLBI VMALLE1IS, R0.

var sysInstFields = map[SpecialOperand]struct{...}{...}

unaryDst var #

var unaryDst = map[obj.As]bool{...}

xcmp var #

var xcmp [C_NCLASS][C_NCLASS]bool

zrReplace var #

zrReplace is the set of instructions for which $0 in the From operand should be replaced with REGZERO.

var zrReplace = map[obj.As]bool{...}

Type Aliases

SpecialOperand type #

go:generate stringer -type SpecialOperand -trimprefix SPOP_

type SpecialOperand int

Structs

Optab struct #

type Optab struct {
as obj.As
a1 uint8
a2 uint8
a3 uint8
a4 uint8
a5 uint8
type_ int8
size_ int8
param int16
flag int8
scond uint8
}

codeBuffer struct #

type codeBuffer struct {
data *[]byte
}

ctxt7 struct #

ctxt7 holds state while assembling a single function. Each function gets a fresh ctxt7. This allows for multiple functions to be safely concurrently assembled.

type ctxt7 struct {
ctxt *obj.Link
newprog obj.ProgAlloc
cursym *obj.LSym
blitrl *obj.Prog
elitrl *obj.Prog
autosize int32
extrasize int32
instoffset int64
pc int64
pool struct{...}
}

Functions

ADR function #

func ADR(p uint32, o uint32, rt uint32) uint32

DRconv function #

func DRconv(a int) string

FPCCMP function #

func FPCCMP(m uint32, s uint32, type_ uint32, op uint32) uint32

FPCMP function #

func FPCMP(m uint32, s uint32, type_ uint32, op uint32, op2 uint32) uint32

FPCVTI function #

func FPCVTI(sf uint32, s uint32, type_ uint32, rmode uint32, op uint32) uint32

FPOP1S function #

func FPOP1S(m uint32, s uint32, type_ uint32, op uint32) uint32

FPOP2S function #

func FPOP2S(m uint32, s uint32, type_ uint32, op uint32) uint32

FPOP3S function #

func FPOP3S(m uint32, s uint32, type_ uint32, op uint32, op2 uint32) uint32

IsAtomicInstruction function #

func IsAtomicInstruction(as obj.As) bool

LD2STR function #

func LD2STR(o uint32) uint32

LDSTR function #

func LDSTR(sz uint32, v uint32, opc uint32) uint32

LDSTX function #

func LDSTX(sz uint32, o2 uint32, l uint32, o1 uint32, o0 uint32) uint32

MOVCONST function #

func MOVCONST(d int64, s int, rt int) uint32

OPBIT function #

func OPBIT(x uint32) uint32

OPBLR function #

func OPBLR(x uint32) uint32

OPBcc function #

func OPBcc(x uint32) uint32

OPDP2 function #

func OPDP2(x uint32) uint32

OPDP3 function #

func OPDP3(sf uint32, op54 uint32, op31 uint32, o0 uint32) uint32

SPCconv function #

func SPCconv(a int64) string

SYSARG4 function #

func SYSARG4(op1 int, Cn int, Cm int, op2 int) int

SYSARG5 function #

form offset parameter to SYS; special register number

func SYSARG5(op0 int, op1 int, Cn int, Cm int, op2 int) int

SYSHINT function #

func SYSHINT(x uint32) uint32

SYSOP function #

func SYSOP(l uint32, op0 uint32, op1 uint32, crn uint32, crm uint32, op2 uint32, rt uint32) uint32

String method #

func (i SpecialOperand) String() string

SysRegEnc function #

func SysRegEnc(r int16) (string, uint32, uint8)

_ function #

func _()

aclass method #

func (c *ctxt7) aclass(a *obj.Addr) int

addLiteralsToPool method #

Adds literal values from the Prog into the literal pool if necessary.

func (c *ctxt7) addLiteralsToPool(p *obj.Prog)

addpool method #

* MOVD foo(SB), R is actually * MOVD addr, REGTMP * MOVD REGTMP, R * where addr is the address of the DWORD containing the address of foo. * * TODO: hash

func (c *ctxt7) addpool(p *obj.Prog, a *obj.Addr)

addrRelocType method #

func (c *ctxt7) addrRelocType(p *obj.Prog) objabi.RelocType

arrange function #

func arrange(a int) string

asmout method #

func (c *ctxt7) asmout(p *obj.Prog, out []uint32) (count int)

asmsizeBytes method #

Return the size of the assembled Prog, in bytes.

func (c *ctxt7) asmsizeBytes(p *obj.Prog) int

autoclass function #

func autoclass(l int64) int

bitconEncode function #

bitconEncode returns the encoding of a bitcon used in logical instructions x is known to be a bitcon a bitcon is a sequence of n ones at low bits (i.e. 1<

func bitconEncode(x uint64, mode int) uint32

brdist method #

func (c *ctxt7) brdist(p *obj.Prog, preshift int, flen int, shift int) int64

buildop function #

func buildop(ctxt *obj.Link)

checkShiftAmount method #

checkShiftAmount checks whether the index shift amount is valid for load with register offset instructions

func (c *ctxt7) checkShiftAmount(p *obj.Prog, a *obj.Addr)

checkUnpredictable method #

checkUnpredictable checks if the source and transfer registers are the same register. ARM64 manual says it is "constrained unpredictable" if the src and dst registers of STP/LDP are same.

func (c *ctxt7) checkUnpredictable(p *obj.Prog, isload bool, wback bool, rn int16, rt1 int16, rt2 int16)

checkindex method #

checkindex checks if index >= 0 && index <= maxindex

func (c *ctxt7) checkindex(p *obj.Prog, index int, maxindex int)

checkoffset method #

checkoffset checks whether the immediate offset is valid for VLD[1-4].P and VST[1-4].P

func (c *ctxt7) checkoffset(p *obj.Prog, as obj.As)

checkpool method #

* when the first reference to the literal pool threatens * to go out of range of a 1Mb PC-relative offset * drop the pool now.

func (c *ctxt7) checkpool(p *obj.Prog)

chipfloat7 method #

chipfloat7() checks if the immediate constants available in FMOVS/FMOVD instructions. For details of the range of constants available, see http://infocenter.arm.com/help/topic/com.arm.doc.dui0473m/dom1359731199385.html.

func (c *ctxt7) chipfloat7(e float64) int

cmp function #

func cmp(a int, b int) bool

con32class method #

con32class reclassifies the constant of 32-bit instruction. Because the constant type is 32-bit, but saved in Offset which type is int64, con32class treats it as uint32 type and reclassifies it.

func (c *ctxt7) con32class(a *obj.Addr) int

con64class method #

con64class reclassifies the constant of C_VCON and C_LCON class.

func (c *ctxt7) con64class(a *obj.Addr) int

emit method #

Write a sequence of opcodes into the code buffer.

func (cb *codeBuffer) emit(op ...uint32)

encRegShiftOrExt method #

encRegShiftOrExt returns the encoding of shifted/extended register, Rx<

func (c *ctxt7) encRegShiftOrExt(p *obj.Prog, a *obj.Addr, r int16) uint32

finish method #

Completes the code buffer for the function by padding the buffer to function alignment with zero values.

func (cb *codeBuffer) finish()

fixUpLongBranch method #

Modify the Prog list if the Prog is a branch with a large offset that cannot be encoded in the instruction. Return true if a modification was made, false if not.

func (c *ctxt7) fixUpLongBranch(p *obj.Prog) bool

flushpool method #

func (c *ctxt7) flushpool(p *obj.Prog)

init function #

func init()

isADDSop function #

func isADDSop(op obj.As) bool

isADDWop function #

func isADDWop(op obj.As) bool

isADDop function #

func isADDop(op obj.As) bool

isANDWop function #

func isANDWop(op obj.As) bool

isANDop function #

func isANDop(op obj.As) bool

isLoadStorePairOp function #

func isLoadStorePairOp(op obj.As) bool

isMOVop function #

func isMOVop(op obj.As) bool

isNEGop function #

func isNEGop(op obj.As) bool

isRegShiftOrExt function #

func isRegShiftOrExt(a *obj.Addr) bool

isRestartable method #

isRestartable returns whether p is a multi-instruction sequence that, if preempted, can be restarted.

func (c *ctxt7) isRestartable(p *obj.Prog) bool

isSTLXRop function #

func isSTLXRop(op obj.As) bool

isSTXPop function #

func isSTXPop(op obj.As) bool

isUnsafePoint method #

isUnsafePoint returns whether p is an unsafe point.

func (c *ctxt7) isUnsafePoint(p *obj.Prog) bool

isaddcon function #

func isaddcon(v int64) bool

isaddcon2 function #

func isaddcon2(v int64) bool

isbitcon function #

isbitcon reports whether a constant can be encoded into a logical instruction. bitcon has a binary form of repetition of a bit sequence of length 2, 4, 8, 16, 32, or 64, which itself is a rotate (w.r.t. the length of the unit) of a sequence of ones. special cases: 0 and -1 are not bitcon. this function needs to run against virtually all the constants, so it needs to be fast. for this reason, bitcon testing and bitcon encoding are separate functions.

func isbitcon(x uint64) bool

ispcdisp function #

ispcdisp reports whether v is a valid PC-relative displacement.

func ispcdisp(v int32) bool

loadStoreClass method #

loadStoreClass reclassifies a load or store operation based on its offset.

func (c *ctxt7) loadStoreClass(p *obj.Prog, lsc int, v int64) int

loadStorePairClass method #

loadStorePairClass reclassifies a load or store pair operation based on its offset.

func (c *ctxt7) loadStorePairClass(p *obj.Prog, lsc int, v int64) int

log2 function #

func log2(x uint64) uint32

maskOpvldvst method #

func (c *ctxt7) maskOpvldvst(p *obj.Prog, o1 uint32) uint32

movcon function #

* if v contains a single 16-bit value aligned * on a 16-bit field, and thus suitable for movk/movn, * return the field index 0 to 3; otherwise return -1.

func movcon(v int64) int

movesize function #

* size in log2(bytes)

func movesize(a obj.As) int

nocache function #

func nocache(p *obj.Prog)

oaddi method #

func (c *ctxt7) oaddi(p *obj.Prog, a obj.As, v int32, rd int16, rn int16) uint32

oaddi12 method #

func (c *ctxt7) oaddi12(p *obj.Prog, v int32, rd int16, rn int16) uint32

ocmp function #

func ocmp(p1 Optab, p2 Optab) int

offsetshift method #

* given an offset v and a class c (see above) * return the offset value to use in the instruction, * scaled if necessary

func (c *ctxt7) offsetshift(p *obj.Prog, v int64, cls int) int64

olsr12u method #

* load/store register (scaled 12-bit unsigned immediate) C3.3.13 * these produce 64-bit values (when there's an option)

func (c *ctxt7) olsr12u(p *obj.Prog, o uint32, v int32, rn int16, rt int16) uint32

olsr9s method #

* load/store register (unscaled 9-bit signed immediate) C3.3.12

func (c *ctxt7) olsr9s(p *obj.Prog, o uint32, v int32, rn int16, rt int16) uint32

olsxrr method #

olsxrr attaches register operands to a load/store opcode supplied in o. The result either encodes a load of r from (r1+r2) or a store of r to (r1+r2).

func (c *ctxt7) olsxrr(p *obj.Prog, o int32, r int, r1 int, r2 int) uint32

omovconst method #

load a constant (MOVCON or BITCON) in a into rt

func (c *ctxt7) omovconst(as obj.As, p *obj.Prog, a *obj.Addr, rt int) (o1 uint32)

omovlconst method #

load a 32-bit/64-bit large constant (LCON or VCON) in a.Offset into rt put the instruction sequence in os and return the number of instructions.

func (c *ctxt7) omovlconst(as obj.As, p *obj.Prog, a *obj.Addr, rt int, os []uint32) (num uint8)

omovlit method #

* load a literal value into dr

func (c *ctxt7) omovlit(as obj.As, p *obj.Prog, a *obj.Addr, dr int) uint32

op0 method #

func (c *ctxt7) op0(p *obj.Prog, a obj.As) uint32

opbfm method #

func (c *ctxt7) opbfm(p *obj.Prog, a obj.As, r int64, s int64, rf int16, rt int16) uint32

opbit method #

func (c *ctxt7) opbit(p *obj.Prog, a obj.As) uint32

opbra method #

* pc-relative branches

func (c *ctxt7) opbra(p *obj.Prog, a obj.As) uint32

opbrr method #

func (c *ctxt7) opbrr(p *obj.Prog, a obj.As) uint32

opextr method #

func (c *ctxt7) opextr(p *obj.Prog, a obj.As, v int64, rn int16, rm int16, rt int16) uint32

opimm method #

func (c *ctxt7) opimm(p *obj.Prog, a obj.As) uint32

opirr method #

* imm -> Rd * imm op Rn -> Rd

func (c *ctxt7) opirr(p *obj.Prog, a obj.As) uint32

opldpstp method #

generate instruction encoding for ldp and stp series

func (c *ctxt7) opldpstp(p *obj.Prog, o *Optab, vo int32, rbase int16, rl int16, rh int16, ldp uint32) uint32

opldr method #

load(immediate) scaled 12-bit unsigned immediate offset. unscaled 9-bit signed immediate offset. pre/post-indexed load. and the 12-bit and 9-bit are distinguished in olsr12u and oslr9s.

func (c *ctxt7) opldr(p *obj.Prog, a obj.As) uint32

opldrr method #

opldrr returns the ARM64 opcode encoding corresponding to the obj.As opcode for load instruction with register offset. The offset register can be (Rn)(Rm.UXTW<<2) or (Rn)(Rm<<2) or (Rn)(Rm).

func (c *ctxt7) opldrr(p *obj.Prog, a obj.As, extension bool) uint32

opload method #

* register offset

func (c *ctxt7) opload(p *obj.Prog, a obj.As) uint32

oplook method #

func (c *ctxt7) oplook(p *obj.Prog) *Optab

oprangeset function #

func oprangeset(a obj.As, t []Optab)

oprrr method #

* basic Rm op Rn -> Rd (using shifted register with 0) * also op Rn -> Rt * also Rm*Rn op Ra -> Rd * also Vm op Vn -> Vd

func (c *ctxt7) oprrr(p *obj.Prog, a obj.As) uint32

opstore method #

func (c *ctxt7) opstore(p *obj.Prog, a obj.As) uint32

opstr method #

store(immediate) scaled 12-bit unsigned immediate offset. unscaled 9-bit signed immediate offset. pre/post-indexed store. and the 12-bit and 9-bit are distinguished in olsr12u and oslr9s.

func (c *ctxt7) opstr(p *obj.Prog, a obj.As) uint32

opstrr method #

opstrr returns the ARM64 opcode encoding corresponding to the obj.As opcode for store instruction with register offset. The offset register can be (Rn)(Rm.UXTW<<2) or (Rn)(Rm<<2) or (Rn)(Rm).

func (c *ctxt7) opstrr(p *obj.Prog, a obj.As, extension bool) uint32

opxrrr method #

* add/subtract sign or zero-extended register

func (c *ctxt7) opxrrr(p *obj.Prog, a obj.As, rd int16, rn int16, rm int16, extend bool) uint32

oregclass function #

func oregclass(l int64) int

pack function #

pack returns the encoding of the "Q" field and two arrangement specifiers.

func pack(q uint32, arngA uint8, arngB uint8) uint32

pc method #

func (cb *codeBuffer) pc() int64

pcAlignPadLength function #

pcAlignPadLength returns the number of bytes required to align pc to alignedValue, reporting an error if alignedValue is not a power of two or is out of range.

func pcAlignPadLength(ctxt *obj.Link, pc int64, alignedValue int64) int

preprocess function #

func preprocess(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc)

progedit function #

func progedit(ctxt *obj.Link, p *obj.Prog, newprog obj.ProgAlloc)

rclass function #

func rclass(r int16) int

rconv function #

func rconv(r int) string

regname function #

func regname(r int) string

regoff method #

func (c *ctxt7) regoff(a *obj.Addr) int32

rewriteToUseGot method #

Rewrite p, if necessary, to access global data via the global offset table.

func (c *ctxt7) rewriteToUseGot(p *obj.Prog)

rlconv function #

func rlconv(list int64) string

roff function #

rm is the Rm register value, o is the extension, amount is the left shift value.

func roff(rm int16, o uint32, amount int16) uint32

roundUp function #

roundUp rounds up x to "to".

func roundUp(x uint32, to uint32) uint32

sequenceOfOnes function #

sequenceOfOnes tests whether a constant is a sequence of ones in binary, with leading and trailing zeros.

func sequenceOfOnes(x uint64) bool

size method #

size returns the size of the sequence of machine instructions when p is encoded with o. Usually it just returns o.size directly, in some cases it checks whether the optimization conditions are met, and if so returns the size of the optimized instruction sequence. These optimizations need to be synchronized with the asmout function.

func (o *Optab) size(ctxt *obj.Link, p *obj.Prog) int

span7 function #

func span7(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc)

splitImm24uScaled function #

splitImm24uScaled splits an immediate into a scaled 12 bit unsigned lo value and an unscaled shifted 12 bit unsigned hi value. These are typically used by adding or subtracting the hi value and using the lo value as the offset for a load or store.

func splitImm24uScaled(v int32, shift int) (int32, int32, error)

stacksplit method #

func (c *ctxt7) stacksplit(p *obj.Prog, framesize int32) *obj.Prog

symAlign function #

symAlign returns the expected symbol alignment of the symbol s. This must match the linker's own default alignment decisions.

func symAlign(s *obj.LSym) int64

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