Imports #
"cmd/internal/obj"
"cmd/internal/obj"
"cmd/internal/obj"
"cmd/internal/objabi"
"fmt"
"log"
"slices"
"cmd/internal/obj"
"fmt"
"cmd/internal/obj"
"cmd/internal/objabi"
"cmd/internal/src"
"cmd/internal/sys"
"internal/abi"
"log"
"math"
"cmd/internal/obj"
"cmd/internal/obj"
"cmd/internal/obj"
"cmd/internal/objabi"
"fmt"
"log"
"slices"
"cmd/internal/obj"
"fmt"
"cmd/internal/obj"
"cmd/internal/objabi"
"cmd/internal/src"
"cmd/internal/sys"
"internal/abi"
"log"
"math"
const AABSD = *ast.BinaryExprconst AABSFconst AADDconst AADDDconst AADDFconst AADDUconst AADDVconst AADDVUconst AADDWconst AAMADDDBVconst AAMADDDBWconst AAMADDVconst AAMADDWconst AAMANDDBVconst AAMANDDBWconst AAMANDVconst AAMANDWconst AAMCASBconst AAMCASDBBconst AAMCASDBHconst AAMCASDBVconst AAMCASDBWconst AAMCASHconst AAMCASVconst AAMCASWconst AAMMAXDBVconst AAMMAXDBVUconst AAMMAXDBWconst AAMMAXDBWUconst AAMMAXVconst AAMMAXVUconst AAMMAXWconst AAMMAXWUconst AAMMINDBVconst AAMMINDBVUconst AAMMINDBWconst AAMMINDBWUconst AAMMINVconst AAMMINVUconst AAMMINWconst AAMMINWUconst AAMORDBVconst AAMORDBWconst AAMORVconst AAMORW2.2.7. Atomic Memory Access Instructions
const AAMSWAPBconst AAMSWAPDBBconst AAMSWAPDBHconst AAMSWAPDBVconst AAMSWAPDBWconst AAMSWAPHconst AAMSWAPVconst AAMSWAPWconst AAMXORDBVconst AAMXORDBWconst AAMXORVconst AAMXORWconst AANDconst AANDNconst ABEQconst ABFPFconst ABFPTconst ABGEconst ABGEUconst ABGEZconst ABGTZ2.2.3.6
const ABITREV4Bconst ABITREV8Bconst ABITREVV2.2.3.7
const ABITREVWconst ABLEZconst ABLTconst ABLTUconst ABLTZconst ABNEconst ABREAKconst ABSTRINSV2.2.3.8
const ABSTRINSWconst ABSTRPICKV2.2.3.9
const ABSTRPICKWconst ACLOV2.2.3.2
const ACLOWconst ACLZVconst ACLZWconst ACMPEQDconst ACMPEQFconst ACMPGEDconst ACMPGEFconst ACMPGTDconst ACMPGTFconst ACPUCFGconst ACRCCWBWconst ACRCCWHWconst ACRCCWVWconst ACRCCWWW2.2.9. CRC Check Instructions
const ACRCWBWconst ACRCWHWconst ACRCWVWconst ACRCWWWconst ACTOVconst ACTOWconst ACTZVconst ACTZWconst ADBARconst ADIVconst ADIVDconst ADIVFconst ADIVUconst ADIVVconst ADIVVUconst ADIVW2.2.3.1
const AEXTWBconst AEXTWHconst AFCLASSD3.2.1.8
const AFCLASSFconst AFCOPYSGD3.2.1.7
const AFCOPYSGFconst AFFINTDVconst AFFINTDWconst AFFINTFV3.2.3.2
const AFFINTFWconst AFLOGBDconst AFLOGBFconst AFMADDD3.2.1.2
const AFMADDFconst AFMAXDconst AFMAXFconst AFMIND3.2.1.3
const AFMINFconst AFMSUBDconst AFMSUBFconst AFNMADDDconst AFNMADDFconst AFNMSUBDconst AFNMSUBFconst AFSCALEBDconst AFSCALEBFconst AFTINTRMVDconst AFTINTRMVFconst AFTINTRMWDconst AFTINTRMWFconst AFTINTRNEVDconst AFTINTRNEVFconst AFTINTRNEWDconst AFTINTRNEWFconst AFTINTRPVDconst AFTINTRPVFconst AFTINTRPWD3.2.3.3
const AFTINTRPWFconst AFTINTRZVDconst AFTINTRZVFconst AFTINTRZWDconst AFTINTRZWFconst AFTINTVDconst AFTINTVFconst AFTINTWDconst AFTINTWFconst AJAL = obj.ACALLconst AJIRLaliases
const AJMP = obj.AJMPconst ALASTconst ALLconst ALLVconst ALU12IWconst ALU32IDconst ALU52IDconst ALUIconst AMASKEQZconst AMASKNEZconst AMOVBconst AMOVBUconst AMOVDconst AMOVDFconst AMOVDVconst AMOVDWconst AMOVFconst AMOVFDconst AMOVFVconst AMOVFWconst AMOVHconst AMOVHU64-bit
const AMOVVconst AMOVVDconst AMOVVFconst AMOVWconst AMOVWDconst AMOVWFconst AMOVWUconst AMULconst AMULDconst AMULFconst AMULHconst AMULHUconst AMULHVconst AMULHVUconst AMULUconst AMULVconst AMULVUconst AMULWconst ANEGDconst ANEGFconst ANEGVconst ANEGWconst ANOOPconst ANORconst AOR2.2.1.8
const AORNconst APCADDU12Iconst APCALAU12Iconst ARDTIMEDconst ARDTIMEHW2.2.10. Other Miscellaneous Instructions
const ARDTIMELWconst AREMconst AREMUconst AREMVconst AREMVUconst ARET = obj.ARETconst AREVB2Hconst AREVB2Wconst AREVB4H2.2.3.4
const AREVBV2.2.3.5
const AREVH2Wconst AREVHVconst ARFEArrangement for Loong64 SIMD instructions
const ARNG_16BArrangement for Loong64 SIMD instructions
const ARNG_16HArrangement for Loong64 SIMD instructions
const ARNG_2QArrangement for Loong64 SIMD instructions
const ARNG_2Varrangement types
const ARNG_32B int16 = iotaArrangement for Loong64 SIMD instructions
const ARNG_4VArrangement for Loong64 SIMD instructions
const ARNG_4WArrangement for Loong64 SIMD instructions
const ARNG_8HArrangement for Loong64 SIMD instructions
const ARNG_8WArrangement for Loong64 SIMD instructions
const ARNG_BArrangement for Loong64 SIMD instructions
const ARNG_BUArrangement for Loong64 SIMD instructions
const ARNG_HArrangement for Loong64 SIMD instructions
const ARNG_HUArrangement for Loong64 SIMD instructions
const ARNG_VArrangement for Loong64 SIMD instructions
const ARNG_VUArrangement for Loong64 SIMD instructions
const ARNG_WArrangement for Loong64 SIMD instructions
const ARNG_WUconst AROTRconst AROTRVconst ASCconst ASCVconst ASGTconst ASGTUconst ASLLconst ASLLVconst ASQRTDconst ASQRTFconst ASRAconst ASRAVconst ASRLconst ASRLVconst ASUBconst ASUBDconst ASUBFconst ASUBUconst ASUBVconst ASUBVUconst ASUBWconst ASYSCALLconst ATEQconst ATNEconst ATRUNCDVconst ATRUNCDW64-bit FP
const ATRUNCFVconst ATRUNCFWLSX and LASX memory access instructions
const AVMOVQLSX and LASX Bit-manipulation Instructions
const AVPCNTBconst AVPCNTHconst AVPCNTVconst AVPCNTWLSX and LASX integer comparison instruction
const AVSEQBconst AVSEQHconst AVSEQVconst AVSEQWconst AWORDconst AXORconst AXVMOVQconst AXVPCNTBconst AXVPCNTHconst AXVPCNTVconst AXVPCNTWconst AXVSEQBconst AXVSEQHconst AXVSEQVconst AXVSEQWvar Anames = []string{...}const BIG = 2046const BRANCH = *ast.BinaryExprgo:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64
const C_ADD0CONgo:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64
const C_ADDCONgo:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64
const C_ADDRgo:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64
const C_AND0CONgo:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64
const C_ANDCONgo:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64
const C_ARNGgo:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64
const C_BRANgo:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64
const C_DACONgo:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64
const C_DCONgo:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64
const C_ELEMgo:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64
const C_EXTADDRgo:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64
const C_FCCREGgo:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64
const C_FCSRREGgo:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64
const C_FREGgo:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64
const C_GOKgo:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64
const C_GOTADDRgo:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64
const C_LACONgo:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64
const C_LAUTOgo:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64
const C_LCONgo:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64
const C_LOREGgo:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64
const C_NCLASSgo:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64
const C_NONE = iotago:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64
const C_REGgo:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64
const C_ROFFgo:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64
const C_SACONgo:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64
const C_SAUTOgo:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64
const C_SCONgo:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64
const C_SOREGgo:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64
const C_TEXTSIZEgo:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64
const C_TLS_IEgo:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64
const C_TLS_LEgo:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64
const C_UCONgo:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64
const C_VREGgo:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64
const C_XREGgo:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64
const C_ZCONgo:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64
const C_ZOREGconst EXT_REG_MASK = 0x1fconst EXT_REG_SHIFT = 0const EXT_SIMDTYPE_MASK = 0x1const EXT_SIMDTYPE_SHIFT = 10const EXT_TYPE_MASK = 0x1fconst EXT_TYPE_SHIFT = 5const FREGRET = REG_F0const FuncAlign = 4mark flags
const LABEL = *ast.BinaryExprLoongArch64 SIMD extension type
const LASXconst LEAF = *ast.BinaryExprvar LOONG64DWARFRegisters = map[int16]int16{...}LoongArch64 SIMD extension type
const LSX int16 = iotavar Linkloong64 = obj.LinkArch{...}const NFREG = 32const NOTUSETMP = *ast.BinaryExprconst NREG = 32const NSNAME = 8const NSYM = 50const NVREG = 32const NXREG = 32const REGARG = *ast.UnaryExprconst REGCTXT = REG_R29const REGG = REG_R22const REGLINK = REG_R1const REGRET = REG_R20const REGRT1 = REG_R20const REGRT2 = REG_R21const REGSP = REG_R3const REGTMP = REG_R30const REGZERO = REG_R0bits 0-4 indicates register: Vn or Xn
bits 5-9 indicates arrangement: 
const REG_ARNG = *ast.BinaryExprbits 0-4 indicates register: Vn or Xn
bits 5-9 indicates arrangement: 
const REG_ELEMbits 0-4 indicates register: Vn or Xn
bits 5-9 indicates arrangement: 
const REG_ELEM_ENDconst REG_F0const REG_F1const REG_F10const REG_F11const REG_F12const REG_F13const REG_F14const REG_F15const REG_F16const REG_F17const REG_F18const REG_F19const REG_F2const REG_F20const REG_F21const REG_F22const REG_F23const REG_F24const REG_F25const REG_F26const REG_F27const REG_F28const REG_F29const REG_F3const REG_F30const REG_F31const REG_F4const REG_F5const REG_F6const REG_F7const REG_F8const REG_F9const REG_FCC0const REG_FCC1const REG_FCC10const REG_FCC11const REG_FCC12const REG_FCC13const REG_FCC14const REG_FCC15const REG_FCC16const REG_FCC17const REG_FCC18const REG_FCC19const REG_FCC2const REG_FCC20const REG_FCC21const REG_FCC22const REG_FCC23const REG_FCC24const REG_FCC25const REG_FCC26const REG_FCC27const REG_FCC28const REG_FCC29const REG_FCC3const REG_FCC30const REG_FCC31const REG_FCC4const REG_FCC5const REG_FCC6const REG_FCC7const REG_FCC8const REG_FCC9const REG_FCSR0const REG_FCSR1const REG_FCSR10const REG_FCSR11const REG_FCSR12const REG_FCSR13const REG_FCSR14const REG_FCSR15const REG_FCSR16const REG_FCSR17const REG_FCSR18const REG_FCSR19const REG_FCSR2const REG_FCSR20const REG_FCSR21const REG_FCSR22const REG_FCSR23const REG_FCSR24const REG_FCSR25const REG_FCSR26const REG_FCSR27const REG_FCSR28const REG_FCSR29const REG_FCSR3const REG_FCSR30const REG_FCSR31const REG_FCSR4const REG_FCSR5const REG_FCSR6const REG_FCSR7const REG_FCSR8const REG_FCSR9const REG_LAST = REG_ELEM_ENDconst REG_R0 = *ast.BinaryExprconst REG_R1const REG_R10const REG_R11const REG_R12const REG_R13const REG_R14const REG_R15const REG_R16const REG_R17const REG_R18const REG_R19const REG_R2const REG_R20const REG_R21const REG_R22const REG_R23const REG_R24const REG_R25const REG_R26const REG_R27const REG_R28const REG_R29const REG_R3const REG_R30const REG_R31const REG_R4const REG_R5const REG_R6const REG_R7const REG_R8const REG_R9const REG_SPECIAL = REG_FCSR0LSX: 128-bit vector register
const REG_V0const REG_V1const REG_V10const REG_V11const REG_V12const REG_V13const REG_V14const REG_V15const REG_V16const REG_V17const REG_V18const REG_V19const REG_V2const REG_V20const REG_V21const REG_V22const REG_V23const REG_V24const REG_V25const REG_V26const REG_V27const REG_V28const REG_V29const REG_V3const REG_V30const REG_V31const REG_V4const REG_V5const REG_V6const REG_V7const REG_V8const REG_V9LASX: 256-bit vector register
const REG_X0const REG_X1const REG_X10const REG_X11const REG_X12const REG_X13const REG_X14const REG_X15const REG_X16const REG_X17const REG_X18const REG_X19const REG_X2const REG_X20const REG_X21const REG_X22const REG_X23const REG_X24const REG_X25const REG_X26const REG_X27const REG_X28const REG_X29const REG_X3const REG_X30const REG_X31const REG_X4const REG_X5const REG_X6const REG_X7const REG_X8const REG_X9const SYNC = *ast.BinaryExprvar atomicInst = map[obj.As]uint32{...}branchLoopHead marks loop entry. Used to insert padding for under-aligned loops.
const branchLoopHeadThis order should be strictly consistent to that in a.out.go.
var cnames0 = []string{...}const loopAlign = 16var oprange [*ast.BinaryExpr][]Optabvar optab = []Optab{...}var xcmp [C_NCLASS][C_NCLASS]booltype Optab struct {
as obj.As
from1 uint8
reg uint8
from3 uint8
to1 uint8
to2 uint8
type_ int8
size int8
param int16
flag uint8
}ctxt0 holds state while assembling a single function. Each function gets a fresh ctxt0. This allows for multiple functions to be safely concurrently assembled.
type ctxt0 struct {
ctxt *obj.Link
newprog obj.ProgAlloc
cursym *obj.LSym
autosize int32
instoffset int64
pc int64
}func DRconv(a int) stringfunc IsAtomicInst(as obj.As) boolfunc OP_12IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32func OP_15I(op uint32, i uint32) uint32func OP_16IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32func OP_16IR_5I(op uint32, i uint32, r2 uint32) uint32Encoding for the 'b' or 'bl' instruction.
func OP_B_BL(op uint32, i uint32) uint32func OP_IR(op uint32, i uint32, r2 uint32) uint32i1 -> msb r2 -> rj i3 -> lsb r4 -> rd
func OP_IRIR(op uint32, i1 uint32, r2 uint32, i3 uint32, r4 uint32) uint32r2 -> rj r3 -> rd
func OP_RR(op uint32, r2 uint32, r3 uint32) uint32r1 -> rk r2 -> rj r3 -> rd
func OP_RRR(op uint32, r1 uint32, r2 uint32, r3 uint32) uint32func OP_RRRR(op uint32, r1 uint32, r2 uint32, r3 uint32, r4 uint32) uint32func (c *ctxt0) aclass(a *obj.Addr) intfunc (c *ctxt0) addnop(p *obj.Prog)func arrange(a int16) stringfunc (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32)func buildop(ctxt *obj.Link)checkindex checks if index >= 0 && index <= maxindex
func (c *ctxt0) checkindex(p *obj.Prog, index uint32, mask uint32)func cmp(a int, b int) boolfunc init()func init()func init()isRestartable returns whether p is a multi-instruction sequence that, if preempted, can be restarted.
func (c *ctxt0) isRestartable(p *obj.Prog) boolisUnsafePoint returns whether p is an unsafe point.
func (c *ctxt0) isUnsafePoint(p *obj.Prog) boolfunc isint32(v int64) boolfunc isuint32(v uint64) boolfunc oclass(a *obj.Addr) intfunc ocmp(p1 Optab, p2 Optab) intfunc (c *ctxt0) opi(a obj.As) uint32func (c *ctxt0) opir(a obj.As) uint32func (c *ctxt0) opirir(a obj.As) uint32func (c *ctxt0) opirr(a obj.As) uint32func (c *ctxt0) oplook(p *obj.Prog) *Optabfunc (c *ctxt0) oprr(a obj.As) uint32func (c *ctxt0) oprrr(a obj.As) uint32func (c *ctxt0) oprrrr(a obj.As) uint32func opset(a obj.As, b0 obj.As)pcAlignPadLength returns the number of bytes required to align pc to alignedValue, reporting an error if alignedValue is not a power of two or is out of range.
func pcAlignPadLength(ctxt *obj.Link, pc int64, alignedValue int64) intfunc prasm(p *obj.Prog)func preprocess(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc)func progedit(ctxt *obj.Link, p *obj.Prog, newprog obj.ProgAlloc)In Loong64,there are 8 CFRs, denoted as fcc0-fcc7. There are 4 FCSRs, denoted as fcsr0-fcsr3.
func (c *ctxt0) rclass(r int16) intfunc rconv(r int) stringfunc (c *ctxt0) regoff(a *obj.Addr) int32func rewriteToUseGot(ctxt *obj.Link, p *obj.Prog, newprog obj.ProgAlloc)func span0(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc)func (c *ctxt0) specialFpMovInst(a obj.As, fclass int, tclass int) uint32func (c *ctxt0) specialLsxMovInst(a obj.As, fReg int16, tReg int16) (op_code uint32, index_mask uint32)func (c *ctxt0) stacksplit(p *obj.Prog, framesize int32) *obj.Progfunc (c *ctxt0) vregoff(a *obj.Addr) int64func vshift(a obj.As) boolGenerated with Arrow