riscv

AADD const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AADD

AADDI const #

2.4: Integer Computational Instructions

const AADDI = *ast.BinaryExpr

AADDIW const #

4.2: Integer Computational Instructions (RV64I)

const AADDIW

AADDUW const #

28.4.1: Address Generation Instructions (Zba)

const AADDUW

AADDW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AADDW

AAMOADDD const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AAMOADDD

AAMOADDW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AAMOADDW

AAMOANDD const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AAMOANDD

AAMOANDW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AAMOANDW

AAMOMAXD const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AAMOMAXD

AAMOMAXUD const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AAMOMAXUD

AAMOMAXUW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AAMOMAXUW

AAMOMAXW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AAMOMAXW

AAMOMIND const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AAMOMIND

AAMOMINUD const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AAMOMINUD

AAMOMINUW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AAMOMINUW

AAMOMINW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AAMOMINW

AAMOORD const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AAMOORD

AAMOORW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AAMOORW

AAMOSWAPD const #

14.4: Atomic Memory Operations (Zaamo)

const AAMOSWAPD

AAMOSWAPW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AAMOSWAPW

AAMOXORD const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AAMOXORD

AAMOXORW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AAMOXORW

AAND const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AAND

AANDI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AANDI

AANDN const #

28.4.2: Basic Bit Manipulation (Zbb)

const AANDN

AAUIPC const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AAUIPC

ABCLR const #

28.4.4: Single-bit Instructions (Zbs)

const ABCLR

ABCLRI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ABCLRI

ABEQ const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ABEQ

ABEQZ const #

Pseudo-instructions. These get translated by the assembler into other instructions, based on their operands.

const ABEQZ

ABEXT const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ABEXT

ABEXTI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ABEXTI

ABGE const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ABGE

ABGEU const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ABGEU

ABGEZ const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ABGEZ

ABGT const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ABGT

ABGTU const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ABGTU

ABGTZ const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ABGTZ

ABINV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ABINV

ABINVI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ABINVI

ABLE const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ABLE

ABLEU const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ABLEU

ABLEZ const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ABLEZ

ABLT const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ABLT

ABLTU const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ABLTU

ABLTZ const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ABLTZ

ABNE const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ABNE

ABNEZ const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ABNEZ

ABSET const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ABSET

ABSETI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ABSETI

ACLZ const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ACLZ

ACLZW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ACLZW

ACPOP const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ACPOP

ACPOPW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ACPOPW

ACSRRC const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ACSRRC

ACSRRCI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ACSRRCI

ACSRRS const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ACSRRS

ACSRRSI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ACSRRSI

ACSRRW const #

7.1: CSR Instructions (Zicsr)

const ACSRRW

ACSRRWI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ACSRRWI

ACTZ const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ACTZ

ACTZW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ACTZW

ADIV const #

13.2: Division Operations

const ADIV

ADIVU const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ADIVU

ADIVUW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ADIVUW

ADIVW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ADIVW

ADRET const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ADRET

AEBREAK const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AEBREAK

AECALL const #

3.3.1: Environment Call and Breakpoint

const AECALL

AFABSD const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFABSD

AFABSS const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFABSS

AFADDD const #

21.4: Double-Precision Floating-Point Computational Instructions

const AFADDD

AFADDQ const #

22.2: Quad-Precision Computational Instructions

const AFADDQ

AFADDS const #

20.6: Single-Precision Floating-Point Computational Instructions

const AFADDS

AFCLASSD const #

21.7: Double-Precision Floating-Point Classify Instruction

const AFCLASSD

AFCLASSQ const #

22.5 Quad-Precision Floating-Point Classify Instruction

const AFCLASSQ

AFCLASSS const #

20.9: Single-Precision Floating-Point Classify Instruction

const AFCLASSS

AFCVTDL const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFCVTDL

AFCVTDLU const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFCVTDLU

AFCVTDQ const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFCVTDQ

AFCVTDS const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFCVTDS

AFCVTDW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFCVTDW

AFCVTDWU const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFCVTDWU

AFCVTLD const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFCVTLD

AFCVTLQ const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFCVTLQ

AFCVTLS const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFCVTLS

AFCVTLUD const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFCVTLUD

AFCVTLUQ const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFCVTLUQ

AFCVTLUS const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFCVTLUS

AFCVTQD const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFCVTQD

AFCVTQL const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFCVTQL

AFCVTQLU const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFCVTQLU

AFCVTQS const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFCVTQS

AFCVTQW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFCVTQW

AFCVTQWU const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFCVTQWU

AFCVTSD const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFCVTSD

AFCVTSL const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFCVTSL

AFCVTSLU const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFCVTSLU

AFCVTSQ const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFCVTSQ

AFCVTSW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFCVTSW

AFCVTSWU const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFCVTSWU

AFCVTWD const #

21.5: Double-Precision Floating-Point Conversion and Move Instructions

const AFCVTWD

AFCVTWQ const #

22.3 Quad-Precision Convert and Move Instructions

const AFCVTWQ

AFCVTWS const #

20.7: Single-Precision Floating-Point Conversion and Move Instructions

const AFCVTWS

AFCVTWUD const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFCVTWUD

AFCVTWUQ const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFCVTWUQ

AFCVTWUS const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFCVTWUS

AFDIVD const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFDIVD

AFDIVQ const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFDIVQ

AFDIVS const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFDIVS

AFENCE const #

2.7: Memory Ordering Instructions

const AFENCE

AFEQD const #

21.6: Double-Precision Floating-Point Compare Instructions

const AFEQD

AFEQQ const #

22.4 Quad-Precision Floating-Point Compare Instructions

const AFEQQ

AFEQS const #

20.8: Single-Precision Floating-Point Compare Instructions

const AFEQS

AFLD const #

21.3: Double-Precision Load and Store Instructions

const AFLD

AFLED const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFLED

AFLEQ const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFLEQ

AFLES const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFLES

AFLQ const #

22.1 Quad-Precision Load and Store Instructions

const AFLQ

AFLTD const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFLTD

AFLTQ const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFLTQ

AFLTS const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFLTS

AFLW const #

20.5: Single-Precision Load and Store Instructions

const AFLW

AFMADDD const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFMADDD

AFMADDQ const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFMADDQ

AFMADDS const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFMADDS

AFMAXD const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFMAXD

AFMAXQ const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFMAXQ

AFMAXS const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFMAXS

AFMIND const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFMIND

AFMINQ const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFMINQ

AFMINS const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFMINS

AFMSUBD const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFMSUBD

AFMSUBQ const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFMSUBQ

AFMSUBS const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFMSUBS

AFMULD const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFMULD

AFMULQ const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFMULQ

AFMULS const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFMULS

AFMVDX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFMVDX

AFMVSX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFMVSX

AFMVWX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFMVWX

AFMVXD const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFMVXD

AFMVXS const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFMVXS

AFMVXW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFMVXW

AFNED const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFNED

AFNEGD const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFNEGD

AFNEGS const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFNEGS

AFNES const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFNES

AFNMADDD const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFNMADDD

AFNMADDQ const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFNMADDQ

AFNMADDS const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFNMADDS

AFNMSUBD const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFNMSUBD

AFNMSUBQ const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFNMSUBQ

AFNMSUBS const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFNMSUBS

AFSD const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFSD

AFSGNJD const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFSGNJD

AFSGNJND const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFSGNJND

AFSGNJNQ const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFSGNJNQ

AFSGNJNS const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFSGNJNS

AFSGNJQ const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFSGNJQ

AFSGNJS const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFSGNJS

AFSGNJXD const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFSGNJXD

AFSGNJXQ const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFSGNJXQ

AFSGNJXS const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFSGNJXS

AFSQ const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFSQ

AFSQRTD const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFSQRTD

AFSQRTQ const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFSQRTQ

AFSQRTS const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFSQRTS

AFSUBD const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFSUBD

AFSUBQ const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFSUBQ

AFSUBS const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFSUBS

AFSW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AFSW

AJAL const #

2.5: Control Transfer Instructions

const AJAL

AJALR const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AJALR

ALAST const #

End marker

const ALAST

ALB const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ALB

ALBU const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ALBU

ALD const #

4.3: Load and Store Instructions (RV64I)

const ALD

ALH const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ALH

ALHU const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ALHU

ALRD const #

14.2: Load-Reserved/Store-Conditional Instructions (Zalrsc)

const ALRD

ALRW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ALRW

ALUI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ALUI

ALW const #

2.6: Load and Store Instructions

const ALW

ALWU const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ALWU

AMAX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AMAX

AMAXU const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AMAXU

AMIN const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AMIN

AMINU const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AMINU

AMOV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AMOV

AMOVB const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AMOVB

AMOVBU const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AMOVBU

AMOVD const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AMOVD

AMOVF const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AMOVF

AMOVH const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AMOVH

AMOVHU const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AMOVHU

AMOVW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AMOVW

AMOVWU const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AMOVWU

AMRET const #

3.3.2: Trap-Return Instructions

const AMRET

AMUL const #

13.1: Multiplication Operations

const AMUL

AMULH const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AMULH

AMULHSU const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AMULHSU

AMULHU const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AMULHU

AMULW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AMULW

ANEG const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ANEG

ANEGW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ANEGW

ANOT const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ANOT

AOR const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AOR

AORCB const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AORCB

AORI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AORI

AORN const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AORN

ARDCYCLE const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ARDCYCLE

ARDINSTRET const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ARDINSTRET

ARDTIME const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ARDTIME

AREM const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AREM

AREMU const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AREMU

AREMUW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AREMUW

AREMW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AREMW

AREV8 const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AREV8

AROL const #

28.4.3: Bitwise Rotation (Zbb)

const AROL

AROLW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AROLW

AROR const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AROR

ARORI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ARORI

ARORIW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ARORIW

ARORW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ARORW

ASB const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ASB

ASBREAK const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ASBREAK

ASCALL const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ASCALL

ASCD const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ASCD

ASCW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ASCW

ASD const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ASD

ASEQZ const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ASEQZ

ASEXTB const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ASEXTB

ASEXTH const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ASEXTH

ASFENCEVMA const #

10.2: Supervisor Memory-Management Fence Instruction

const ASFENCEVMA

ASH const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ASH

ASH1ADD const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ASH1ADD

ASH1ADDUW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ASH1ADDUW

ASH2ADD const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ASH2ADD

ASH2ADDUW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ASH2ADDUW

ASH3ADD const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ASH3ADD

ASH3ADDUW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ASH3ADDUW

ASLL const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ASLL

ASLLI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ASLLI

ASLLIUW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ASLLIUW

ASLLIW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ASLLIW

ASLLW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ASLLW

ASLT const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ASLT

ASLTI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ASLTI

ASLTIU const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ASLTIU

ASLTU const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ASLTU

ASNEZ const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ASNEZ

ASRA const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ASRA

ASRAI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ASRAI

ASRAIW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ASRAIW

ASRAW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ASRAW

ASRET const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ASRET

ASRL const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ASRL

ASRLI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ASRLI

ASRLIW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ASRLIW

ASRLW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ASRLW

ASUB const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ASUB

ASUBW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ASUBW

ASW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const ASW

AVAADDUVV const #

31.12.2. Vector Single-Width Averaging Add and Subtract

const AVAADDUVV

AVAADDUVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVAADDUVX

AVAADDVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVAADDVV

AVAADDVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVAADDVX

AVADCVIM const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVADCVIM

AVADCVVM const #

31.11.4. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions

const AVADCVVM

AVADCVXM const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVADCVXM

AVADDVI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVADDVI

AVADDVV const #

31.11.1. Vector Single-Width Integer Add and Subtract

const AVADDVV

AVADDVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVADDVX

AVANDVI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVANDVI

AVANDVV const #

31.11.5. Vector Bitwise Logical Instructions

const AVANDVV

AVANDVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVANDVX

AVASUBUVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVASUBUVV

AVASUBUVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVASUBUVX

AVASUBVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVASUBVV

AVASUBVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVASUBVX

AVCOMPRESSVM const #

31.16.5. Vector Compress Instruction

const AVCOMPRESSVM

AVCPOPM const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVCPOPM

AVDIVUVV const #

31.11.11. Vector Integer Divide Instructions

const AVDIVUVV

AVDIVUVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVDIVUVX

AVDIVVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVDIVVV

AVDIVVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVDIVVX

AVFADDVF const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFADDVF

AVFADDVV const #

31.13.2. Vector Single-Width Floating-Point Add/Subtract Instructions

const AVFADDVV

AVFCLASSV const #

31.13.14. Vector Floating-Point Classify Instruction

const AVFCLASSV

AVFCVTFXUV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFCVTFXUV

AVFCVTFXV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFCVTFXV

AVFCVTRTZXFV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFCVTRTZXFV

AVFCVTRTZXUFV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFCVTRTZXUFV

AVFCVTXFV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFCVTXFV

AVFCVTXUFV const #

31.13.17. Single-Width Floating-Point/Integer Type-Convert Instructions

const AVFCVTXUFV

AVFDIVVF const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFDIVVF

AVFDIVVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFDIVVV

AVFIRSTM const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFIRSTM

AVFMACCVF const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFMACCVF

AVFMACCVV const #

31.13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions

const AVFMACCVV

AVFMADDVF const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFMADDVF

AVFMADDVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFMADDVV

AVFMAXVF const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFMAXVF

AVFMAXVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFMAXVV

AVFMERGEVFM const #

31.13.15. Vector Floating-Point Merge Instruction

const AVFMERGEVFM

AVFMINVF const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFMINVF

AVFMINVV const #

31.13.11. Vector Floating-Point MIN/MAX Instructions

const AVFMINVV

AVFMSACVF const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFMSACVF

AVFMSACVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFMSACVV

AVFMSUBVF const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFMSUBVF

AVFMSUBVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFMSUBVV

AVFMULVF const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFMULVF

AVFMULVV const #

31.13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions

const AVFMULVV

AVFMVFS const #

31.16.2. Floating-Point Scalar Move Instructions

const AVFMVFS

AVFMVSF const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFMVSF

AVFMVVF const #

31.13.16. Vector Floating-Point Move Instruction

const AVFMVVF

AVFNCVTFFW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFNCVTFFW

AVFNCVTFXUW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFNCVTFXUW

AVFNCVTFXW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFNCVTFXW

AVFNCVTRODFFW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFNCVTRODFFW

AVFNCVTRTZXFW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFNCVTRTZXFW

AVFNCVTRTZXUFW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFNCVTRTZXUFW

AVFNCVTXFW const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFNCVTXFW

AVFNCVTXUFW const #

31.13.19. Narrowing Floating-Point/Integer Type-Convert Instructions

const AVFNCVTXUFW

AVFNMACCVF const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFNMACCVF

AVFNMACCVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFNMACCVV

AVFNMADDVF const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFNMADDVF

AVFNMADDVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFNMADDVV

AVFNMSACVF const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFNMSACVF

AVFNMSACVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFNMSACVV

AVFNMSUBVF const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFNMSUBVF

AVFNMSUBVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFNMSUBVV

AVFRDIVVF const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFRDIVVF

AVFREC7V const #

31.13.10. Vector Floating-Point Reciprocal Estimate Instruction

const AVFREC7V

AVFREDMAXVS const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFREDMAXVS

AVFREDMINVS const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFREDMINVS

AVFREDOSUMVS const #

31.14.3. Vector Single-Width Floating-Point Reduction Instructions

const AVFREDOSUMVS

AVFREDUSUMVS const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFREDUSUMVS

AVFRSQRT7V const #

31.13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction

const AVFRSQRT7V

AVFRSUBVF const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFRSUBVF

AVFSGNJNVF const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFSGNJNVF

AVFSGNJNVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFSGNJNVV

AVFSGNJVF const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFSGNJVF

AVFSGNJVV const #

31.13.12. Vector Floating-Point Sign-Injection Instructions

const AVFSGNJVV

AVFSGNJXVF const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFSGNJXVF

AVFSGNJXVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFSGNJXVV

AVFSLIDE1DOWNVF const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFSLIDE1DOWNVF

AVFSLIDE1UPVF const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFSLIDE1UPVF

AVFSQRTV const #

31.13.8. Vector Floating-Point Square-Root Instruction

const AVFSQRTV

AVFSUBVF const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFSUBVF

AVFSUBVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFSUBVV

AVFWADDVF const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFWADDVF

AVFWADDVV const #

31.13.3. Vector Widening Floating-Point Add/Subtract Instructions

const AVFWADDVV

AVFWADDWF const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFWADDWF

AVFWADDWV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFWADDWV

AVFWCVTFFV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFWCVTFFV

AVFWCVTFXUV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFWCVTFXUV

AVFWCVTFXV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFWCVTFXV

AVFWCVTRTZXFV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFWCVTRTZXFV

AVFWCVTRTZXUFV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFWCVTRTZXUFV

AVFWCVTXFV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFWCVTXFV

AVFWCVTXUFV const #

31.13.18. Widening Floating-Point/Integer Type-Convert Instructions

const AVFWCVTXUFV

AVFWMACCVF const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFWMACCVF

AVFWMACCVV const #

31.13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions

const AVFWMACCVV

AVFWMSACVF const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFWMSACVF

AVFWMSACVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFWMSACVV

AVFWMULVF const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFWMULVF

AVFWMULVV const #

31.13.5. Vector Widening Floating-Point Multiply

const AVFWMULVV

AVFWNMACCVF const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFWNMACCVF

AVFWNMACCVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFWNMACCVV

AVFWNMSACVF const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFWNMSACVF

AVFWNMSACVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFWNMSACVV

AVFWREDOSUMVS const #

31.14.4. Vector Widening Floating-Point Reduction Instructions

const AVFWREDOSUMVS

AVFWREDUSUMVS const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFWREDUSUMVS

AVFWSUBVF const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFWSUBVF

AVFWSUBVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFWSUBVV

AVFWSUBWF const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFWSUBWF

AVFWSUBWV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVFWSUBWV

AVIDV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVIDV

AVIOTAM const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVIOTAM

AVL1RE16V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVL1RE16V

AVL1RE32V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVL1RE32V

AVL1RE64V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVL1RE64V

AVL1RE8V const #

31.7.9. Vector Load/Store Whole Register Instructions

const AVL1RE8V

AVL2RE16V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVL2RE16V

AVL2RE32V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVL2RE32V

AVL2RE64V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVL2RE64V

AVL2RE8V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVL2RE8V

AVL4RE16V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVL4RE16V

AVL4RE32V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVL4RE32V

AVL4RE64V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVL4RE64V

AVL4RE8V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVL4RE8V

AVL8RE16V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVL8RE16V

AVL8RE32V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVL8RE32V

AVL8RE64V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVL8RE64V

AVL8RE8V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVL8RE8V

AVLE16FFV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVLE16FFV

AVLE16V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVLE16V

AVLE32FFV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVLE32FFV

AVLE32V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVLE32V

AVLE64FFV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVLE64FFV

AVLE64V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVLE64V

AVLE8FFV const #

31.7.7. Unit-stride Fault-Only-First Loads

const AVLE8FFV

AVLE8V const #

31.7.4. Vector Unit-Stride Instructions

const AVLE8V

AVLMV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVLMV

AVLOXEI16V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVLOXEI16V

AVLOXEI32V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVLOXEI32V

AVLOXEI64V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVLOXEI64V

AVLOXEI8V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVLOXEI8V

AVLSE16V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVLSE16V

AVLSE32V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVLSE32V

AVLSE64V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVLSE64V

AVLSE8V const #

31.7.5. Vector Strided Instructions

const AVLSE8V

AVLUXEI16V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVLUXEI16V

AVLUXEI32V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVLUXEI32V

AVLUXEI64V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVLUXEI64V

AVLUXEI8V const #

31.7.6. Vector Indexed Instructions

const AVLUXEI8V

AVMACCVV const #

31.11.13. Vector Single-Width Integer Multiply-Add Instructions

const AVMACCVV

AVMACCVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMACCVX

AVMADCVI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMADCVI

AVMADCVIM const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMADCVIM

AVMADCVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMADCVV

AVMADCVVM const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMADCVVM

AVMADCVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMADCVX

AVMADCVXM const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMADCVXM

AVMADDVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMADDVV

AVMADDVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMADDVX

AVMANDMM const #

31.15. Vector Mask Instructions

const AVMANDMM

AVMANDNMM const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMANDNMM

AVMAXUVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMAXUVV

AVMAXUVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMAXUVX

AVMAXVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMAXVV

AVMAXVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMAXVX

AVMERGEVIM const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMERGEVIM

AVMERGEVVM const #

31.11.15. Vector Integer Merge Instructions

const AVMERGEVVM

AVMERGEVXM const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMERGEVXM

AVMFEQVF const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMFEQVF

AVMFEQVV const #

31.13.13. Vector Floating-Point Compare Instructions

const AVMFEQVV

AVMFGEVF const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMFGEVF

AVMFGTVF const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMFGTVF

AVMFLEVF const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMFLEVF

AVMFLEVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMFLEVV

AVMFLTVF const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMFLTVF

AVMFLTVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMFLTVV

AVMFNEVF const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMFNEVF

AVMFNEVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMFNEVV

AVMINUVV const #

31.11.9. Vector Integer Min/Max Instructions

const AVMINUVV

AVMINUVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMINUVX

AVMINVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMINVV

AVMINVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMINVX

AVMNANDMM const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMNANDMM

AVMNORMM const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMNORMM

AVMORMM const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMORMM

AVMORNMM const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMORNMM

AVMSBCVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMSBCVV

AVMSBCVVM const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMSBCVVM

AVMSBCVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMSBCVX

AVMSBCVXM const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMSBCVXM

AVMSBFM const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMSBFM

AVMSEQVI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMSEQVI

AVMSEQVV const #

31.11.8. Vector Integer Compare Instructions

const AVMSEQVV

AVMSEQVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMSEQVX

AVMSGTUVI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMSGTUVI

AVMSGTUVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMSGTUVX

AVMSGTVI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMSGTVI

AVMSGTVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMSGTVX

AVMSIFM const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMSIFM

AVMSLEUVI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMSLEUVI

AVMSLEUVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMSLEUVV

AVMSLEUVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMSLEUVX

AVMSLEVI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMSLEVI

AVMSLEVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMSLEVV

AVMSLEVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMSLEVX

AVMSLTUVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMSLTUVV

AVMSLTUVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMSLTUVX

AVMSLTVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMSLTVV

AVMSLTVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMSLTVX

AVMSNEVI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMSNEVI

AVMSNEVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMSNEVV

AVMSNEVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMSNEVX

AVMSOFM const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMSOFM

AVMULHSUVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMULHSUVV

AVMULHSUVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMULHSUVX

AVMULHUVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMULHUVV

AVMULHUVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMULHUVX

AVMULHVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMULHVV

AVMULHVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMULHVX

AVMULVV const #

31.11.10. Vector Single-Width Integer Multiply Instructions

const AVMULVV

AVMULVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMULVX

AVMV1RV const #

31.16.6. Whole Vector Register Move

const AVMV1RV

AVMV2RV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMV2RV

AVMV4RV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMV4RV

AVMV8RV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMV8RV

AVMVSX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMVSX

AVMVVI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMVVI

AVMVVV const #

31.11.16. Vector Integer Move Instructions

const AVMVVV

AVMVVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMVVX

AVMVXS const #

31.16.1. Integer Scalar Move Instructions

const AVMVXS

AVMXNORMM const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMXNORMM

AVMXORMM const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVMXORMM

AVNCLIPUWI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVNCLIPUWI

AVNCLIPUWV const #

31.12.5. Vector Narrowing Fixed-Point Clip Instructions

const AVNCLIPUWV

AVNCLIPUWX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVNCLIPUWX

AVNCLIPWI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVNCLIPWI

AVNCLIPWV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVNCLIPWV

AVNCLIPWX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVNCLIPWX

AVNMSACVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVNMSACVV

AVNMSACVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVNMSACVX

AVNMSUBVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVNMSUBVV

AVNMSUBVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVNMSUBVX

AVNSRAWI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVNSRAWI

AVNSRAWV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVNSRAWV

AVNSRAWX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVNSRAWX

AVNSRLWI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVNSRLWI

AVNSRLWV const #

31.11.7. Vector Narrowing Integer Right Shift Instructions

const AVNSRLWV

AVNSRLWX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVNSRLWX

AVORVI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVORVI

AVORVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVORVV

AVORVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVORVX

AVREDANDVS const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVREDANDVS

AVREDMAXUVS const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVREDMAXUVS

AVREDMAXVS const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVREDMAXVS

AVREDMINUVS const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVREDMINUVS

AVREDMINVS const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVREDMINVS

AVREDORVS const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVREDORVS

AVREDSUMVS const #

31.14.1. Vector Single-Width Integer Reduction Instructions

const AVREDSUMVS

AVREDXORVS const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVREDXORVS

AVREMUVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVREMUVV

AVREMUVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVREMUVX

AVREMVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVREMVV

AVREMVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVREMVX

AVRGATHEREI16VV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVRGATHEREI16VV

AVRGATHERVI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVRGATHERVI

AVRGATHERVV const #

31.16.4. Vector Register Gather Instructions

const AVRGATHERVV

AVRGATHERVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVRGATHERVX

AVRSUBVI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVRSUBVI

AVRSUBVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVRSUBVX

AVS1RV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVS1RV

AVS2RV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVS2RV

AVS4RV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVS4RV

AVS8RV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVS8RV

AVSADDUVI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSADDUVI

AVSADDUVV const #

31.12.1. Vector Single-Width Saturating Add and Subtract

const AVSADDUVV

AVSADDUVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSADDUVX

AVSADDVI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSADDVI

AVSADDVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSADDVV

AVSADDVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSADDVX

AVSBCVVM const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSBCVVM

AVSBCVXM const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSBCVXM

AVSE16V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSE16V

AVSE32V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSE32V

AVSE64V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSE64V

AVSE8V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSE8V

AVSETIVLI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSETIVLI

AVSETVL const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSETVL

AVSETVLI const #

31.6. Configuration-Setting Instructions

const AVSETVLI

AVSEXTVF2 const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSEXTVF2

AVSEXTVF4 const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSEXTVF4

AVSEXTVF8 const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSEXTVF8

AVSLIDE1DOWNVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSLIDE1DOWNVX

AVSLIDE1UPVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSLIDE1UPVX

AVSLIDEDOWNVI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSLIDEDOWNVI

AVSLIDEDOWNVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSLIDEDOWNVX

AVSLIDEUPVI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSLIDEUPVI

AVSLIDEUPVX const #

31.16.3. Vector Slide Instructions

const AVSLIDEUPVX

AVSLLVI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSLLVI

AVSLLVV const #

31.11.6. Vector Single-Width Shift Instructions

const AVSLLVV

AVSLLVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSLLVX

AVSMULVV const #

31.12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation

const AVSMULVV

AVSMULVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSMULVX

AVSMV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSMV

AVSOXEI16V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSOXEI16V

AVSOXEI32V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSOXEI32V

AVSOXEI64V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSOXEI64V

AVSOXEI8V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSOXEI8V

AVSRAVI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSRAVI

AVSRAVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSRAVV

AVSRAVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSRAVX

AVSRLVI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSRLVI

AVSRLVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSRLVV

AVSRLVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSRLVX

AVSSE16V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSSE16V

AVSSE32V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSSE32V

AVSSE64V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSSE64V

AVSSE8V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSSE8V

AVSSRAVI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSSRAVI

AVSSRAVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSSRAVV

AVSSRAVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSSRAVX

AVSSRLVI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSSRLVI

AVSSRLVV const #

31.12.4. Vector Single-Width Scaling Shift Instructions

const AVSSRLVV

AVSSRLVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSSRLVX

AVSSUBUVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSSUBUVV

AVSSUBUVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSSUBUVX

AVSSUBVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSSUBVV

AVSSUBVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSSUBVX

AVSUBVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSUBVV

AVSUBVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSUBVX

AVSUXEI16V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSUXEI16V

AVSUXEI32V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSUXEI32V

AVSUXEI64V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSUXEI64V

AVSUXEI8V const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVSUXEI8V

AVWADDUVV const #

31.11.2. Vector Widening Integer Add/Subtract

const AVWADDUVV

AVWADDUVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVWADDUVX

AVWADDUWV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVWADDUWV

AVWADDUWX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVWADDUWX

AVWADDVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVWADDVV

AVWADDVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVWADDVX

AVWADDWV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVWADDWV

AVWADDWX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVWADDWX

AVWMACCSUVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVWMACCSUVV

AVWMACCSUVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVWMACCSUVX

AVWMACCUSVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVWMACCUSVX

AVWMACCUVV const #

31.11.14. Vector Widening Integer Multiply-Add Instructions

const AVWMACCUVV

AVWMACCUVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVWMACCUVX

AVWMACCVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVWMACCVV

AVWMACCVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVWMACCVX

AVWMULSUVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVWMULSUVV

AVWMULSUVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVWMULSUVX

AVWMULUVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVWMULUVV

AVWMULUVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVWMULUVX

AVWMULVV const #

31.11.12. Vector Widening Integer Multiply Instructions

const AVWMULVV

AVWMULVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVWMULVX

AVWREDSUMUVS const #

31.14.2. Vector Widening Integer Reduction Instructions

const AVWREDSUMUVS

AVWREDSUMVS const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVWREDSUMVS

AVWSUBUVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVWSUBUVV

AVWSUBUVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVWSUBUVX

AVWSUBUWV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVWSUBUWV

AVWSUBUWX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVWSUBUWX

AVWSUBVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVWSUBVV

AVWSUBVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVWSUBVX

AVWSUBWV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVWSUBWV

AVWSUBWX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVWSUBWX

AVXORVI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVXORVI

AVXORVV const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVXORVV

AVXORVX const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVXORVX

AVZEXTVF2 const #

31.11.3. Vector Integer Extension

const AVZEXTVF2

AVZEXTVF4 const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVZEXTVF4

AVZEXTVF8 const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AVZEXTVF8

AWFI const #

3.3.3: Wait for Interrupt

const AWFI

AWORD const #

The escape hatch. Inserts a single 32-bit word.

const AWORD

AXNOR const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AXNOR

AXOR const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AXOR

AXORI const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AXORI

AZEXTH const #

RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files at https://github.com/riscv/riscv-opcodes. As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/. If you modify this table, you MUST run 'go generate' to regenerate anames.go!

const AZEXTH

Anames var #

var Anames = []string{...}

BTypeImmMask const #

BTypeImmMask is a mask including only the immediate portion of B-type instructions.

const BTypeImmMask = 0xfe000f80

CBTypeImmMask const #

CBTypeImmMask is a mask including only the immediate portion of CB-type instructions.

const CBTypeImmMask = 0x1c7c

CJTypeImmMask const #

CJTypeImmMask is a mask including only the immediate portion of CJ-type instructions.

const CJTypeImmMask = 0x1f7c

ITypeImmMask const #

ITypeImmMask is a mask including only the immediate portion of I-type instructions.

const ITypeImmMask = 0xfff00000

JTypeImmMask const #

JTypeImmMask is a mask including only the immediate portion of J-type instructions.

const JTypeImmMask = 0xfffff000

LinkRISCV64 var #

var LinkRISCV64 = obj.LinkArch{...}

NEED_CALL_RELOC const #

NEED_CALL_RELOC is set on an AUIPC instruction to indicate that it is the first instruction in an AUIPC + JAL pair that needs a R_RISCV_CALL relocation.

const NEED_CALL_RELOC

NEED_JAL_RELOC const #

NEED_JAL_RELOC is set on JAL instructions to indicate that a R_RISCV_JAL relocation is needed.

const NEED_JAL_RELOC

NEED_PCREL_ITYPE_RELOC const #

NEED_PCREL_ITYPE_RELOC is set on AUIPC instructions to indicate that it is the first instruction in an AUIPC + I-type pair that needs a R_RISCV_PCREL_ITYPE relocation.

const NEED_PCREL_ITYPE_RELOC

NEED_PCREL_STYPE_RELOC const #

NEED_PCREL_STYPE_RELOC is set on AUIPC instructions to indicate that it is the first instruction in an AUIPC + S-type pair that needs a R_RISCV_PCREL_STYPE relocation.

const NEED_PCREL_STYPE_RELOC

REGG const #

const REGG = REG_G

REGSP const #

Names generated by the SSA compiler.

const REGSP = REG_SP

REG_A0 const #

const REG_A0 = REG_X10

REG_A1 const #

const REG_A1 = REG_X11

REG_A2 const #

const REG_A2 = REG_X12

REG_A3 const #

const REG_A3 = REG_X13

REG_A4 const #

const REG_A4 = REG_X14

REG_A5 const #

const REG_A5 = REG_X15

REG_A6 const #

const REG_A6 = REG_X16

REG_A7 const #

const REG_A7 = REG_X17

REG_CTXT const #

Go runtime register names.

const REG_CTXT = REG_S10

REG_END const #

This marks the end of the register numbering.

const REG_END

REG_F0 const #

Floating Point register numberings.

const REG_F0

REG_F1 const #

const REG_F1

REG_F10 const #

const REG_F10

REG_F11 const #

const REG_F11

REG_F12 const #

const REG_F12

REG_F13 const #

const REG_F13

REG_F14 const #

const REG_F14

REG_F15 const #

const REG_F15

REG_F16 const #

const REG_F16

REG_F17 const #

const REG_F17

REG_F18 const #

const REG_F18

REG_F19 const #

const REG_F19

REG_F2 const #

const REG_F2

REG_F20 const #

const REG_F20

REG_F21 const #

const REG_F21

REG_F22 const #

const REG_F22

REG_F23 const #

const REG_F23

REG_F24 const #

const REG_F24

REG_F25 const #

const REG_F25

REG_F26 const #

const REG_F26

REG_F27 const #

const REG_F27

REG_F28 const #

const REG_F28

REG_F29 const #

const REG_F29

REG_F3 const #

const REG_F3

REG_F30 const #

const REG_F30

REG_F31 const #

const REG_F31

REG_F4 const #

const REG_F4

REG_F5 const #

const REG_F5

REG_F6 const #

const REG_F6

REG_F7 const #

const REG_F7

REG_F8 const #

const REG_F8

REG_F9 const #

const REG_F9

REG_FA0 const #

const REG_FA0 = REG_F10

REG_FA1 const #

const REG_FA1 = REG_F11

REG_FA2 const #

const REG_FA2 = REG_F12

REG_FA3 const #

const REG_FA3 = REG_F13

REG_FA4 const #

const REG_FA4 = REG_F14

REG_FA5 const #

const REG_FA5 = REG_F15

REG_FA6 const #

const REG_FA6 = REG_F16

REG_FA7 const #

const REG_FA7 = REG_F17

REG_FS0 const #

const REG_FS0 = REG_F8

REG_FS1 const #

const REG_FS1 = REG_F9

REG_FS10 const #

const REG_FS10 = REG_F26

REG_FS11 const #

const REG_FS11 = REG_F27

REG_FS2 const #

const REG_FS2 = REG_F18

REG_FS3 const #

const REG_FS3 = REG_F19

REG_FS4 const #

const REG_FS4 = REG_F20

REG_FS5 const #

const REG_FS5 = REG_F21

REG_FS6 const #

const REG_FS6 = REG_F22

REG_FS7 const #

const REG_FS7 = REG_F23

REG_FS8 const #

const REG_FS8 = REG_F24

REG_FS9 const #

const REG_FS9 = REG_F25

REG_FT0 const #

ABI names for floating point registers.

const REG_FT0 = REG_F0

REG_FT1 const #

const REG_FT1 = REG_F1

REG_FT10 const #

const REG_FT10 = REG_F30

REG_FT11 const #

const REG_FT11 = REG_F31

REG_FT2 const #

const REG_FT2 = REG_F2

REG_FT3 const #

const REG_FT3 = REG_F3

REG_FT4 const #

const REG_FT4 = REG_F4

REG_FT5 const #

const REG_FT5 = REG_F5

REG_FT6 const #

const REG_FT6 = REG_F6

REG_FT7 const #

const REG_FT7 = REG_F7

REG_FT8 const #

const REG_FT8 = REG_F28

REG_FT9 const #

const REG_FT9 = REG_F29

REG_G const #

const REG_G = REG_S11

REG_GP const #

const REG_GP = REG_X3

REG_LR const #

const REG_LR = REG_RA

REG_RA const #

const REG_RA = REG_X1

REG_S0 const #

const REG_S0 = REG_X8

REG_S1 const #

const REG_S1 = REG_X9

REG_S10 const #

const REG_S10 = REG_X26

REG_S11 const #

const REG_S11 = REG_X27

REG_S2 const #

const REG_S2 = REG_X18

REG_S3 const #

const REG_S3 = REG_X19

REG_S4 const #

const REG_S4 = REG_X20

REG_S5 const #

const REG_S5 = REG_X21

REG_S6 const #

const REG_S6 = REG_X22

REG_S7 const #

const REG_S7 = REG_X23

REG_S8 const #

const REG_S8 = REG_X24

REG_S9 const #

const REG_S9 = REG_X25

REG_SP const #

const REG_SP = REG_X2

REG_T0 const #

const REG_T0 = REG_X5

REG_T1 const #

const REG_T1 = REG_X6

REG_T2 const #

const REG_T2 = REG_X7

REG_T3 const #

const REG_T3 = REG_X28

REG_T4 const #

const REG_T4 = REG_X29

REG_T5 const #

const REG_T5 = REG_X30

REG_T6 const #

const REG_T6 = REG_X31

REG_TMP const #

const REG_TMP = REG_T6

REG_TP const #

const REG_TP = REG_X4

REG_V0 const #

Vector register numberings.

const REG_V0

REG_V1 const #

const REG_V1

REG_V10 const #

const REG_V10

REG_V11 const #

const REG_V11

REG_V12 const #

const REG_V12

REG_V13 const #

const REG_V13

REG_V14 const #

const REG_V14

REG_V15 const #

const REG_V15

REG_V16 const #

const REG_V16

REG_V17 const #

const REG_V17

REG_V18 const #

const REG_V18

REG_V19 const #

const REG_V19

REG_V2 const #

const REG_V2

REG_V20 const #

const REG_V20

REG_V21 const #

const REG_V21

REG_V22 const #

const REG_V22

REG_V23 const #

const REG_V23

REG_V24 const #

const REG_V24

REG_V25 const #

const REG_V25

REG_V26 const #

const REG_V26

REG_V27 const #

const REG_V27

REG_V28 const #

const REG_V28

REG_V29 const #

const REG_V29

REG_V3 const #

const REG_V3

REG_V30 const #

const REG_V30

REG_V31 const #

const REG_V31

REG_V4 const #

const REG_V4

REG_V5 const #

const REG_V5

REG_V6 const #

const REG_V6

REG_V7 const #

const REG_V7

REG_V8 const #

const REG_V8

REG_V9 const #

const REG_V9

REG_X0 const #

Base register numberings.

const REG_X0 = *ast.BinaryExpr

REG_X1 const #

const REG_X1

REG_X10 const #

const REG_X10

REG_X11 const #

const REG_X11

REG_X12 const #

const REG_X12

REG_X13 const #

const REG_X13

REG_X14 const #

const REG_X14

REG_X15 const #

const REG_X15

REG_X16 const #

const REG_X16

REG_X17 const #

const REG_X17

REG_X18 const #

const REG_X18

REG_X19 const #

const REG_X19

REG_X2 const #

const REG_X2

REG_X20 const #

const REG_X20

REG_X21 const #

const REG_X21

REG_X22 const #

const REG_X22

REG_X23 const #

const REG_X23

REG_X24 const #

const REG_X24

REG_X25 const #

const REG_X25

REG_X26 const #

const REG_X26

REG_X27 const #

const REG_X27

REG_X28 const #

const REG_X28

REG_X29 const #

const REG_X29

REG_X3 const #

const REG_X3

REG_X30 const #

const REG_X30

REG_X31 const #

const REG_X31

REG_X4 const #

const REG_X4

REG_X5 const #

const REG_X5

REG_X6 const #

const REG_X6

REG_X7 const #

const REG_X7

REG_X8 const #

const REG_X8

REG_X9 const #

const REG_X9

REG_ZERO const #

General registers reassigned to ABI names.

const REG_ZERO = REG_X0

RISCV64DWARFRegisters var #

https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-dwarf.adoc#dwarf-register-numbers

var RISCV64DWARFRegisters = map[int16]int16{...}

RM_RDN const #

const RM_RDN

RM_RMM const #

const RM_RMM

RM_RNE const #

const RM_RNE uint8 = iota

RM_RTZ const #

const RM_RTZ

RM_RUP const #

const RM_RUP

STypeImmMask const #

STypeImmMask is a mask including only the immediate portion of S-type instructions.

const STypeImmMask = 0xfe000f80

USES_REG_TMP const #

USES_REG_TMP indicates that a machine instruction generated from the corresponding *obj.Prog uses the temporary register.

const USES_REG_TMP = *ast.BinaryExpr

UTypeImmMask const #

UTypeImmMask is a mask including only the immediate portion of U-type instructions.

const UTypeImmMask = 0xfffff000

bEncoding var #

var bEncoding = encoding{...}

badEncoding var #

badEncoding is used when an invalid op is encountered. An error has already been generated, so let anything else through.

var badEncoding = encoding{...}

iFEncoding var #

var iFEncoding = encoding{...}

iIIEncoding var #

var iIIEncoding = encoding{...}

instructions var #

instructions contains details of RISC-V instructions, including their encoding type. Entries are masked with obj.AMask to keep indices small.

var instructions = [*ast.BinaryExpr]instructionData{...}

jEncoding var #

var jEncoding = encoding{...}

pseudoOpEncoding var #

pseudoOpEncoding panics if encoding is attempted, but does no validation.

var pseudoOpEncoding = encoding{...}

rFFEncoding var #

var rFFEncoding = encoding{...}

rFFFEncoding var #

var rFFFEncoding = encoding{...}

rFFFFEncoding var #

var rFFFFEncoding = encoding{...}

rFFIEncoding var #

var rFFIEncoding = encoding{...}

rFIEncoding var #

var rFIEncoding = encoding{...}

rIFEncoding var #

var rIFEncoding = encoding{...}

rIIEncoding var #

var rIIEncoding = encoding{...}

rIIIEncoding var #

var rIIIEncoding = encoding{...}

rawEncoding var #

rawEncoding encodes a raw instruction byte sequence.

var rawEncoding = encoding{...}

rmSuffixBit const #

const rmSuffixBit uint8 = *ast.BinaryExpr

rmSuffixSet var #

opSuffix encoding to uint8 which fit into p.Scond

var rmSuffixSet = map[string]uint8{...}

sFEncoding var #

var sFEncoding = encoding{...}

sIEncoding var #

var sIEncoding = encoding{...}

uEncoding var #

var uEncoding = encoding{...}

unaryDst var #

All unary instructions which write to their arguments (as opposed to reading from them) go here. The assembly parser uses this information to populate its AST in a semantically reasonable way. Any instructions not listed here are assumed to either be non-unary or to read from its argument.

var unaryDst = map[obj.As]bool{...}