arm64asm

Imports

Imports # 

"encoding/binary"
"fmt"
"strings"
"fmt"
"strings"
"fmt"
"io"
"sort"
"strings"

Constants & Variables

ABS const # 

const ABS

ADC const # 

const ADC

ADCS const # 

const ADCS

ADD const # 

const ADD

ADDHN const # 

const ADDHN

ADDHN2 const # 

const ADDHN2

ADDP const # 

const ADDP

ADDS const # 

const ADDS

ADDV const # 

const ADDV

ADR const # 

const ADR

ADRP const # 

const ADRP

AESD const # 

const AESD

AESE const # 

const AESE

AESIMC const # 

const AESIMC

AESMC const # 

const AESMC

AND const # 

const AND

ANDS const # 

const ANDS

ASR const # 

const ASR

ASRV const # 

const ASRV

AT const # 

const AT

AddrOffset const # 

const AddrOffset

AddrPostIndex const # 

const AddrPostIndex

AddrPostReg const # 

const AddrPostReg

AddrPreIndex const # 

const AddrPreIndex

Arrangement16B const # 

const Arrangement16B

Arrangement1D const # 

const Arrangement1D

Arrangement1Q const # 

const Arrangement1Q

Arrangement2D const # 

const Arrangement2D

Arrangement2S const # 

const Arrangement2S

Arrangement4H const # 

const Arrangement4H

Arrangement4S const # 

const Arrangement4S

Arrangement8B const # 

const Arrangement8B

Arrangement8H const # 

const Arrangement8H

ArrangementB const # 

const ArrangementB

ArrangementD const # 

const ArrangementD

ArrangementH const # 

const ArrangementH

ArrangementS const # 

const ArrangementS

B const # 

const B

B0 const # 

const B0

B1 const # 

const B1

B10 const # 

const B10

B11 const # 

const B11

B12 const # 

const B12

B13 const # 

const B13

B14 const # 

const B14

B15 const # 

const B15

B16 const # 

const B16

B17 const # 

const B17

B18 const # 

const B18

B19 const # 

const B19

B2 const # 

const B2

B20 const # 

const B20

B21 const # 

const B21

B22 const # 

const B22

B23 const # 

const B23

B24 const # 

const B24

B25 const # 

const B25

B26 const # 

const B26

B27 const # 

const B27

B28 const # 

const B28

B29 const # 

const B29

B3 const # 

const B3

B30 const # 

const B30

B31 const # 

const B31

B4 const # 

const B4

B5 const # 

const B5

B6 const # 

const B6

B7 const # 

const B7

B8 const # 

const B8

B9 const # 

const B9

BFI const # 

const BFI

BFM const # 

const BFM

BFXIL const # 

const BFXIL

BIC const # 

const BIC

BICS const # 

const BICS

BIF const # 

const BIF

BIT const # 

const BIT

BL const # 

const BL

BLR const # 

const BLR

BR const # 

const BR

BRK const # 

const BRK

BSL const # 

const BSL

CBNZ const # 

const CBNZ

CBZ const # 

const CBZ

CCMN const # 

const CCMN

CCMP const # 

const CCMP

CINC const # 

const CINC

CINV const # 

const CINV

CLREX const # 

const CLREX

CLS const # 

const CLS

CLZ const # 

const CLZ

CMEQ const # 

const CMEQ

CMGE const # 

const CMGE

CMGT const # 

const CMGT

CMHI const # 

const CMHI

CMHS const # 

const CMHS

CMLE const # 

const CMLE

CMLT const # 

const CMLT

CMN const # 

const CMN

CMP const # 

const CMP

CMTST const # 

const CMTST

CNEG const # 

const CNEG

CNT const # 

const CNT

CRC32B const # 

const CRC32B

CRC32CB const # 

const CRC32CB

CRC32CH const # 

const CRC32CH

CRC32CW const # 

const CRC32CW

CRC32CX const # 

const CRC32CX

CRC32H const # 

const CRC32H

CRC32W const # 

const CRC32W

CRC32X const # 

const CRC32X

CSEL const # 

const CSEL

CSET const # 

const CSET

CSETM const # 

const CSETM

CSINC const # 

const CSINC

CSINV const # 

const CSINV

CSNEG const # 

const CSNEG

D0 const # 

const D0

D1 const # 

const D1

D10 const # 

const D10

D11 const # 

const D11

D12 const # 

const D12

D13 const # 

const D13

D14 const # 

const D14

D15 const # 

const D15

D16 const # 

const D16

D17 const # 

const D17

D18 const # 

const D18

D19 const # 

const D19

D2 const # 

const D2

D20 const # 

const D20

D21 const # 

const D21

D22 const # 

const D22

D23 const # 

const D23

D24 const # 

const D24

D25 const # 

const D25

D26 const # 

const D26

D27 const # 

const D27

D28 const # 

const D28

D29 const # 

const D29

D3 const # 

const D3

D30 const # 

const D30

D31 const # 

const D31

D4 const # 

const D4

D5 const # 

const D5

D6 const # 

const D6

D7 const # 

const D7

D8 const # 

const D8

D9 const # 

const D9

DAIFClr const # 

const DAIFClr

DAIFSet const # 

const DAIFSet

DC const # 

const DC

DCPS1 const # 

const DCPS1

DCPS2 const # 

const DCPS2

DCPS3 const # 

const DCPS3

DMB const # 

const DMB

DRPS const # 

const DRPS

DSB const # 

const DSB

DUP const # 

const DUP

EON const # 

const EON

EOR const # 

const EOR

ERET const # 

const ERET

EXT const # 

const EXT

EXTR const # 

const EXTR

FABD const # 

const FABD

FABS const # 

const FABS

FACGE const # 

const FACGE

FACGT const # 

const FACGT

FADD const # 

const FADD

FADDP const # 

const FADDP

FCCMP const # 

const FCCMP

FCCMPE const # 

const FCCMPE

FCMEQ const # 

const FCMEQ

FCMGE const # 

const FCMGE

FCMGT const # 

const FCMGT

FCMLE const # 

const FCMLE

FCMLT const # 

const FCMLT

FCMP const # 

const FCMP

FCMPE const # 

const FCMPE

FCSEL const # 

const FCSEL

FCVT const # 

const FCVT

FCVTAS const # 

const FCVTAS

FCVTAU const # 

const FCVTAU

FCVTL const # 

const FCVTL

FCVTL2 const # 

const FCVTL2

FCVTMS const # 

const FCVTMS

FCVTMU const # 

const FCVTMU

FCVTN const # 

const FCVTN

FCVTN2 const # 

const FCVTN2

FCVTNS const # 

const FCVTNS

FCVTNU const # 

const FCVTNU

FCVTPS const # 

const FCVTPS

FCVTPU const # 

const FCVTPU

FCVTXN const # 

const FCVTXN

FCVTXN2 const # 

const FCVTXN2

FCVTZS const # 

const FCVTZS

FCVTZU const # 

const FCVTZU

FDIV const # 

const FDIV

FMADD const # 

const FMADD

FMAX const # 

const FMAX

FMAXNM const # 

const FMAXNM

FMAXNMP const # 

const FMAXNMP

FMAXNMV const # 

const FMAXNMV

FMAXP const # 

const FMAXP

FMAXV const # 

const FMAXV

FMIN const # 

const FMIN

FMINNM const # 

const FMINNM

FMINNMP const # 

const FMINNMP

FMINNMV const # 

const FMINNMV

FMINP const # 

const FMINP

FMINV const # 

const FMINV

FMLA const # 

const FMLA

FMLS const # 

const FMLS

FMOV const # 

const FMOV

FMSUB const # 

const FMSUB

FMUL const # 

const FMUL

FMULX const # 

const FMULX

FNEG const # 

const FNEG

FNMADD const # 

const FNMADD

FNMSUB const # 

const FNMSUB

FNMUL const # 

const FNMUL

FRECPE const # 

const FRECPE

FRECPS const # 

const FRECPS

FRECPX const # 

const FRECPX

FRINTA const # 

const FRINTA

FRINTI const # 

const FRINTI

FRINTM const # 

const FRINTM

FRINTN const # 

const FRINTN

FRINTP const # 

const FRINTP

FRINTX const # 

const FRINTX

FRINTZ const # 

const FRINTZ

FRSQRTE const # 

const FRSQRTE

FRSQRTS const # 

const FRSQRTS

FSQRT const # 

const FSQRT

FSUB const # 

const FSUB

H0 const # 

const H0

H1 const # 

const H1

H10 const # 

const H10

H11 const # 

const H11

H12 const # 

const H12

H13 const # 

const H13

H14 const # 

const H14

H15 const # 

const H15

H16 const # 

const H16

H17 const # 

const H17

H18 const # 

const H18

H19 const # 

const H19

H2 const # 

const H2

H20 const # 

const H20

H21 const # 

const H21

H22 const # 

const H22

H23 const # 

const H23

H24 const # 

const H24

H25 const # 

const H25

H26 const # 

const H26

H27 const # 

const H27

H28 const # 

const H28

H29 const # 

const H29

H3 const # 

const H3

H30 const # 

const H30

H31 const # 

const H31

H4 const # 

const H4

H5 const # 

const H5

H6 const # 

const H6

H7 const # 

const H7

H8 const # 

const H8

H9 const # 

const H9

HINT const # 

const HINT

HLT const # 

const HLT

HVC const # 

const HVC

IC const # 

const IC

INS const # 

const INS

ISB const # 

const ISB

LD1 const # 

const LD1

LD1R const # 

const LD1R

LD2 const # 

const LD2

LD2R const # 

const LD2R

LD3 const # 

const LD3

LD3R const # 

const LD3R

LD4 const # 

const LD4

LD4R const # 

const LD4R

LDAR const # 

const LDAR

LDARB const # 

const LDARB

LDARH const # 

const LDARH

LDAXP const # 

const LDAXP

LDAXR const # 

const LDAXR

LDAXRB const # 

const LDAXRB

LDAXRH const # 

const LDAXRH

LDNP const # 

const LDNP

LDP const # 

const LDP

LDPSW const # 

const LDPSW

LDR const # 

const LDR

LDRB const # 

const LDRB

LDRH const # 

const LDRH

LDRSB const # 

const LDRSB

LDRSH const # 

const LDRSH

LDRSW const # 

const LDRSW

LDTR const # 

const LDTR

LDTRB const # 

const LDTRB

LDTRH const # 

const LDTRH

LDTRSB const # 

const LDTRSB

LDTRSH const # 

const LDTRSH

LDTRSW const # 

const LDTRSW

LDUR const # 

const LDUR

LDURB const # 

const LDURB

LDURH const # 

const LDURH

LDURSB const # 

const LDURSB

LDURSH const # 

const LDURSH

LDURSW const # 

const LDURSW

LDXP const # 

const LDXP

LDXR const # 

const LDXR

LDXRB const # 

const LDXRB

LDXRH const # 

const LDXRH

LSL const # 

const LSL

LSLV const # 

const LSLV

LSR const # 

const LSR

LSRV const # 

const LSRV

MADD const # 

const MADD

MLA const # 

const MLA

MLS const # 

const MLS

MNEG const # 

const MNEG

MOV const # 

const MOV

MOVI const # 

const MOVI

MOVK const # 

const MOVK

MOVN const # 

const MOVN

MOVZ const # 

const MOVZ

MRS const # 

const MRS

MSR const # 

const MSR

MSUB const # 

const MSUB

MUL const # 

const MUL

MVN const # 

const MVN

MVNI const # 

const MVNI

NEG const # 

const NEG

NEGS const # 

const NEGS

NGC const # 

const NGC

NGCS const # 

const NGCS

NOP const # 

const NOP

NOT const # 

const NOT

ORN const # 

const ORN

ORR const # 

const ORR

PMUL const # 

const PMUL

PMULL const # 

const PMULL

PMULL2 const # 

const PMULL2

PRFM const # 

const PRFM

PRFUM const # 

const PRFUM

Q0 const # 

const Q0

Q1 const # 

const Q1

Q10 const # 

const Q10

Q11 const # 

const Q11

Q12 const # 

const Q12

Q13 const # 

const Q13

Q14 const # 

const Q14

Q15 const # 

const Q15

Q16 const # 

const Q16

Q17 const # 

const Q17

Q18 const # 

const Q18

Q19 const # 

const Q19

Q2 const # 

const Q2

Q20 const # 

const Q20

Q21 const # 

const Q21

Q22 const # 

const Q22

Q23 const # 

const Q23

Q24 const # 

const Q24

Q25 const # 

const Q25

Q26 const # 

const Q26

Q27 const # 

const Q27

Q28 const # 

const Q28

Q29 const # 

const Q29

Q3 const # 

const Q3

Q30 const # 

const Q30

Q31 const # 

const Q31

Q4 const # 

const Q4

Q5 const # 

const Q5

Q6 const # 

const Q6

Q7 const # 

const Q7

Q8 const # 

const Q8

Q9 const # 

const Q9

RADDHN const # 

const RADDHN

RADDHN2 const # 

const RADDHN2

RBIT const # 

const RBIT

RET const # 

const RET

REV const # 

const REV

REV16 const # 

const REV16

REV32 const # 

const REV32

REV64 const # 

const REV64

ROR const # 

const ROR

RORV const # 

const RORV

RSHRN const # 

const RSHRN

RSHRN2 const # 

const RSHRN2

RSUBHN const # 

const RSUBHN

RSUBHN2 const # 

const RSUBHN2

S0 const # 

const S0

S1 const # 

const S1

S10 const # 

const S10

S11 const # 

const S11

S12 const # 

const S12

S13 const # 

const S13

S14 const # 

const S14

S15 const # 

const S15

S16 const # 

const S16

S17 const # 

const S17

S18 const # 

const S18

S19 const # 

const S19

S2 const # 

const S2

S20 const # 

const S20

S21 const # 

const S21

S22 const # 

const S22

S23 const # 

const S23

S24 const # 

const S24

S25 const # 

const S25

S26 const # 

const S26

S27 const # 

const S27

S28 const # 

const S28

S29 const # 

const S29

S3 const # 

const S3

S30 const # 

const S30

S31 const # 

const S31

S4 const # 

const S4

S5 const # 

const S5

S6 const # 

const S6

S7 const # 

const S7

S8 const # 

const S8

S9 const # 

const S9

SABA const # 

const SABA

SABAL const # 

const SABAL

SABAL2 const # 

const SABAL2

SABD const # 

const SABD

SABDL const # 

const SABDL

SABDL2 const # 

const SABDL2

SADALP const # 

const SADALP

SADDL const # 

const SADDL

SADDL2 const # 

const SADDL2

SADDLP const # 

const SADDLP

SADDLV const # 

const SADDLV

SADDW const # 

const SADDW

SADDW2 const # 

const SADDW2

SBC const # 

const SBC

SBCS const # 

const SBCS

SBFIZ const # 

const SBFIZ

SBFM const # 

const SBFM

SBFX const # 

const SBFX

SCVTF const # 

const SCVTF

SDIV const # 

const SDIV

SEV const # 

const SEV

SEVL const # 

const SEVL

SHA1C const # 

const SHA1C

SHA1H const # 

const SHA1H

SHA1M const # 

const SHA1M

SHA1P const # 

const SHA1P

SHA1SU0 const # 

const SHA1SU0

SHA1SU1 const # 

const SHA1SU1

SHA256H const # 

const SHA256H

SHA256H2 const # 

const SHA256H2

SHA256SU0 const # 

const SHA256SU0

SHA256SU1 const # 

const SHA256SU1

SHADD const # 

const SHADD

SHL const # 

const SHL

SHLL const # 

const SHLL

SHLL2 const # 

const SHLL2

SHRN const # 

const SHRN

SHRN2 const # 

const SHRN2

SHSUB const # 

const SHSUB

SLI const # 

const SLI

SMADDL const # 

const SMADDL

SMAX const # 

const SMAX

SMAXP const # 

const SMAXP

SMAXV const # 

const SMAXV

SMC const # 

const SMC

SMIN const # 

const SMIN

SMINP const # 

const SMINP

SMINV const # 

const SMINV

SMLAL const # 

const SMLAL

SMLAL2 const # 

const SMLAL2

SMLSL const # 

const SMLSL

SMLSL2 const # 

const SMLSL2

SMNEGL const # 

const SMNEGL

SMOV const # 

const SMOV

SMSUBL const # 

const SMSUBL

SMULH const # 

const SMULH

SMULL const # 

const SMULL

SMULL2 const # 

const SMULL2

SP const # 

const SP = XZR

SPSel const # 

const SPSel Pstatefield = iota

SQABS const # 

const SQABS

SQADD const # 

const SQADD

SQDMLAL const # 

const SQDMLAL

SQDMLAL2 const # 

const SQDMLAL2

SQDMLSL const # 

const SQDMLSL

SQDMLSL2 const # 

const SQDMLSL2

SQDMULH const # 

const SQDMULH

SQDMULL const # 

const SQDMULL

SQDMULL2 const # 

const SQDMULL2

SQNEG const # 

const SQNEG

SQRDMULH const # 

const SQRDMULH

SQRSHL const # 

const SQRSHL

SQRSHRN const # 

const SQRSHRN

SQRSHRN2 const # 

const SQRSHRN2

SQRSHRUN const # 

const SQRSHRUN

SQRSHRUN2 const # 

const SQRSHRUN2

SQSHL const # 

const SQSHL

SQSHLU const # 

const SQSHLU

SQSHRN const # 

const SQSHRN

SQSHRN2 const # 

const SQSHRN2

SQSHRUN const # 

const SQSHRUN

SQSHRUN2 const # 

const SQSHRUN2

SQSUB const # 

const SQSUB

SQXTN const # 

const SQXTN

SQXTN2 const # 

const SQXTN2

SQXTUN const # 

const SQXTUN

SQXTUN2 const # 

const SQXTUN2

SRHADD const # 

const SRHADD

SRI const # 

const SRI

SRSHL const # 

const SRSHL

SRSHR const # 

const SRSHR

SRSRA const # 

const SRSRA

SSHL const # 

const SSHL

SSHLL const # 

const SSHLL

SSHLL2 const # 

const SSHLL2

SSHR const # 

const SSHR

SSRA const # 

const SSRA

SSUBL const # 

const SSUBL

SSUBL2 const # 

const SSUBL2

SSUBW const # 

const SSUBW

SSUBW2 const # 

const SSUBW2

ST1 const # 

const ST1

ST2 const # 

const ST2

ST3 const # 

const ST3

ST4 const # 

const ST4

STLR const # 

const STLR

STLRB const # 

const STLRB

STLRH const # 

const STLRH

STLXP const # 

const STLXP

STLXR const # 

const STLXR

STLXRB const # 

const STLXRB

STLXRH const # 

const STLXRH

STNP const # 

const STNP

STP const # 

const STP

STR const # 

const STR

STRB const # 

const STRB

STRH const # 

const STRH

STTR const # 

const STTR

STTRB const # 

const STTRB

STTRH const # 

const STTRH

STUR const # 

const STUR

STURB const # 

const STURB

STURH const # 

const STURH

STXP const # 

const STXP

STXR const # 

const STXR

STXRB const # 

const STXRB

STXRH const # 

const STXRH

SUB const # 

const SUB

SUBHN const # 

const SUBHN

SUBHN2 const # 

const SUBHN2

SUBS const # 

const SUBS

SUQADD const # 

const SUQADD

SVC const # 

const SVC

SXTB const # 

const SXTB

SXTH const # 

const SXTH

SXTL const # 

const SXTL

SXTL2 const # 

const SXTL2

SXTW const # 

const SXTW

SYS const # 

const SYS

SYSL const # 

const SYSL

TBL const # 

const TBL

TBNZ const # 

const TBNZ

TBX const # 

const TBX

TBZ const # 

const TBZ

TLBI const # 

const TLBI

TRN1 const # 

const TRN1

TRN2 const # 

const TRN2

TST const # 

const TST

UABA const # 

const UABA

UABAL const # 

const UABAL

UABAL2 const # 

const UABAL2

UABD const # 

const UABD

UABDL const # 

const UABDL

UABDL2 const # 

const UABDL2

UADALP const # 

const UADALP

UADDL const # 

const UADDL

UADDL2 const # 

const UADDL2

UADDLP const # 

const UADDLP

UADDLV const # 

const UADDLV

UADDW const # 

const UADDW

UADDW2 const # 

const UADDW2

UBFIZ const # 

const UBFIZ

UBFM const # 

const UBFM

UBFX const # 

const UBFX

UCVTF const # 

const UCVTF

UDIV const # 

const UDIV

UHADD const # 

const UHADD

UHSUB const # 

const UHSUB

UMADDL const # 

const UMADDL

UMAX const # 

const UMAX

UMAXP const # 

const UMAXP

UMAXV const # 

const UMAXV

UMIN const # 

const UMIN

UMINP const # 

const UMINP

UMINV const # 

const UMINV

UMLAL const # 

const UMLAL

UMLAL2 const # 

const UMLAL2

UMLSL const # 

const UMLSL

UMLSL2 const # 

const UMLSL2

UMNEGL const # 

const UMNEGL

UMOV const # 

const UMOV

UMSUBL const # 

const UMSUBL

UMULH const # 

const UMULH

UMULL const # 

const UMULL

UMULL2 const # 

const UMULL2

UQADD const # 

const UQADD

UQRSHL const # 

const UQRSHL

UQRSHRN const # 

const UQRSHRN

UQRSHRN2 const # 

const UQRSHRN2

UQSHL const # 

const UQSHL

UQSHRN const # 

const UQSHRN

UQSHRN2 const # 

const UQSHRN2

UQSUB const # 

const UQSUB

UQXTN const # 

const UQXTN

UQXTN2 const # 

const UQXTN2

URECPE const # 

const URECPE

URHADD const # 

const URHADD

URSHL const # 

const URSHL

URSHR const # 

const URSHR

URSQRTE const # 

const URSQRTE

URSRA const # 

const URSRA

USHL const # 

const USHL

USHLL const # 

const USHLL

USHLL2 const # 

const USHLL2

USHR const # 

const USHR

USQADD const # 

const USQADD

USRA const # 

const USRA

USUBL const # 

const USUBL

USUBL2 const # 

const USUBL2

USUBW const # 

const USUBW

USUBW2 const # 

const USUBW2

UXTB const # 

const UXTB

UXTH const # 

const UXTH

UXTL const # 

const UXTL

UXTL2 const # 

const UXTL2

UZP1 const # 

const UZP1

UZP2 const # 

const UZP2

V0 const # 

const V0

V1 const # 

const V1

V10 const # 

const V10

V11 const # 

const V11

V12 const # 

const V12

V13 const # 

const V13

V14 const # 

const V14

V15 const # 

const V15

V16 const # 

const V16

V17 const # 

const V17

V18 const # 

const V18

V19 const # 

const V19

V2 const # 

const V2

V20 const # 

const V20

V21 const # 

const V21

V22 const # 

const V22

V23 const # 

const V23

V24 const # 

const V24

V25 const # 

const V25

V26 const # 

const V26

V27 const # 

const V27

V28 const # 

const V28

V29 const # 

const V29

V3 const # 

const V3

V30 const # 

const V30

V31 const # 

const V31

V4 const # 

const V4

V5 const # 

const V5

V6 const # 

const V6

V7 const # 

const V7

V8 const # 

const V8

V9 const # 

const V9

W0 const # 

const W0 Reg = iota

W1 const # 

const W1

W10 const # 

const W10

W11 const # 

const W11

W12 const # 

const W12

W13 const # 

const W13

W14 const # 

const W14

W15 const # 

const W15

W16 const # 

const W16

W17 const # 

const W17

W18 const # 

const W18

W19 const # 

const W19

W2 const # 

const W2

W20 const # 

const W20

W21 const # 

const W21

W22 const # 

const W22

W23 const # 

const W23

W24 const # 

const W24

W25 const # 

const W25

W26 const # 

const W26

W27 const # 

const W27

W28 const # 

const W28

W29 const # 

const W29

W3 const # 

const W3

W30 const # 

const W30

W4 const # 

const W4

W5 const # 

const W5

W6 const # 

const W6

W7 const # 

const W7

W8 const # 

const W8

W9 const # 

const W9

WFE const # 

const WFE

WFI const # 

const WFI

WSP const # 

const WSP = WZR

WZR const # 

const WZR

X0 const # 

const X0

X1 const # 

const X1

X10 const # 

const X10

X11 const # 

const X11

X12 const # 

const X12

X13 const # 

const X13

X14 const # 

const X14

X15 const # 

const X15

X16 const # 

const X16

X17 const # 

const X17

X18 const # 

const X18

X19 const # 

const X19

X2 const # 

const X2

X20 const # 

const X20

X21 const # 

const X21

X22 const # 

const X22

X23 const # 

const X23

X24 const # 

const X24

X25 const # 

const X25

X26 const # 

const X26

X27 const # 

const X27

X28 const # 

const X28

X29 const # 

const X29

X3 const # 

const X3

X30 const # 

const X30

X4 const # 

const X4

X5 const # 

const X5

X6 const # 

const X6

X7 const # 

const X7

X8 const # 

const X8

X9 const # 

const X9

XTN const # 

const XTN

XTN2 const # 

const XTN2

XZR const # 

const XZR

YIELD const # 

const YIELD

ZIP1 const # 

const ZIP1

ZIP2 const # 

const ZIP2

_ const # 

const _ Arrangement = iota

_ const # 

const _ AddrMode = iota

_ const # 

const _ ExtShift = iota

_ const # 

const _ instArg = iota

_ const # 

const _ Op = iota

arg_Bt const # 

const arg_Bt

arg_Cm const # 

const arg_Cm

arg_Cn const # 

const arg_Cn

arg_Da const # 

const arg_Da

arg_Dd const # 

const arg_Dd

arg_Dm const # 

const arg_Dm

arg_Dn const # 

const arg_Dn

arg_Dt const # 

const arg_Dt

arg_Dt2 const # 

const arg_Dt2

arg_Hd const # 

const arg_Hd

arg_Hn const # 

const arg_Hn

arg_Ht const # 

const arg_Ht

arg_IAddSub const # 

const arg_IAddSub

arg_Qd const # 

const arg_Qd

arg_Qn const # 

const arg_Qn

arg_Qt const # 

const arg_Qt

arg_Qt2 const # 

const arg_Qt2

arg_Rm_extend__UXTB_0__UXTH_1__UXTW_2__LSL_UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4 const # 

const arg_Rm_extend__UXTB_0__UXTH_1__UXTW_2__LSL_UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4

arg_Rn_16_5__W_1__W_2__W_4__X_8 const # 

const arg_Rn_16_5__W_1__W_2__W_4__X_8

arg_Rt_31_1__W_0__X_1 const # 

const arg_Rt_31_1__W_0__X_1

arg_Sa const # 

const arg_Sa

arg_Sd const # 

const arg_Sd

arg_Sm const # 

const arg_Sm

arg_Sn const # 

const arg_Sn

arg_St const # 

const arg_St

arg_St2 const # 

const arg_St2

arg_Vd_16_5__B_1__H_2__S_4__D_8 const # 

const arg_Vd_16_5__B_1__H_2__S_4__D_8

arg_Vd_19_4__B_1__H_2__S_4 const # 

const arg_Vd_19_4__B_1__H_2__S_4

arg_Vd_19_4__B_1__H_2__S_4__D_8 const # 

const arg_Vd_19_4__B_1__H_2__S_4__D_8

arg_Vd_19_4__D_8 const # 

const arg_Vd_19_4__D_8

arg_Vd_19_4__S_4__D_8 const # 

const arg_Vd_19_4__S_4__D_8

arg_Vd_22_1__S_0 const # 

const arg_Vd_22_1__S_0

arg_Vd_22_1__S_0__D_1 const # 

const arg_Vd_22_1__S_0__D_1

arg_Vd_22_1__S_1 const # 

const arg_Vd_22_1__S_1

arg_Vd_22_2__B_0__H_1__S_2 const # 

const arg_Vd_22_2__B_0__H_1__S_2

arg_Vd_22_2__B_0__H_1__S_2__D_3 const # 

const arg_Vd_22_2__B_0__H_1__S_2__D_3

arg_Vd_22_2__D_3 const # 

const arg_Vd_22_2__D_3

arg_Vd_22_2__H_0__S_1__D_2 const # 

const arg_Vd_22_2__H_0__S_1__D_2

arg_Vd_22_2__H_1__S_2 const # 

const arg_Vd_22_2__H_1__S_2

arg_Vd_22_2__S_1__D_2 const # 

const arg_Vd_22_2__S_1__D_2

arg_Vd_arrangement_16B const # 

const arg_Vd_arrangement_16B

arg_Vd_arrangement_2D const # 

const arg_Vd_arrangement_2D

arg_Vd_arrangement_4S const # 

const arg_Vd_arrangement_4S

arg_Vd_arrangement_D_index__1 const # 

const arg_Vd_arrangement_D_index__1

arg_Vd_arrangement_Q___2S_0__4S_1 const # 

const arg_Vd_arrangement_Q___2S_0__4S_1

arg_Vd_arrangement_Q___4H_0__8H_1 const # 

const arg_Vd_arrangement_Q___4H_0__8H_1

arg_Vd_arrangement_Q___8B_0__16B_1 const # 

const arg_Vd_arrangement_Q___8B_0__16B_1

arg_Vd_arrangement_Q_sz___2S_00__4S_10__2D_11 const # 

const arg_Vd_arrangement_Q_sz___2S_00__4S_10__2D_11

arg_Vd_arrangement_imm5_Q___8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81 const # 

const arg_Vd_arrangement_imm5_Q___8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81

arg_Vd_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4__imm5lt4gt_8_1 const # 

const arg_Vd_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4__imm5lt4gt_8_1

arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__2S_40__4S_41__2D_81 const # 

const arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__2S_40__4S_41__2D_81

arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41 const # 

const arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41

arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81 const # 

const arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81

arg_Vd_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4 const # 

const arg_Vd_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4

arg_Vd_arrangement_size_Q___4H_00__8H_01__2S_10__4S_11__1D_20__2D_21 const # 

const arg_Vd_arrangement_size_Q___4H_00__8H_01__2S_10__4S_11__1D_20__2D_21

arg_Vd_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21 const # 

const arg_Vd_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21

arg_Vd_arrangement_size_Q___8B_00__16B_01 const # 

const arg_Vd_arrangement_size_Q___8B_00__16B_01

arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11 const # 

const arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11

arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21 const # 

const arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21

arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31 const # 

const arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31

arg_Vd_arrangement_size___4S_1__2D_2 const # 

const arg_Vd_arrangement_size___4S_1__2D_2

arg_Vd_arrangement_size___8H_0__1Q_3 const # 

const arg_Vd_arrangement_size___8H_0__1Q_3

arg_Vd_arrangement_size___8H_0__4S_1__2D_2 const # 

const arg_Vd_arrangement_size___8H_0__4S_1__2D_2

arg_Vd_arrangement_sz_Q___2S_00__4S_01 const # 

const arg_Vd_arrangement_sz_Q___2S_00__4S_01

arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11 const # 

const arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11

arg_Vd_arrangement_sz_Q___2S_10__4S_11 const # 

const arg_Vd_arrangement_sz_Q___2S_10__4S_11

arg_Vd_arrangement_sz_Q___4H_00__8H_01__2S_10__4S_11 const # 

const arg_Vd_arrangement_sz_Q___4H_00__8H_01__2S_10__4S_11

arg_Vd_arrangement_sz___4S_0__2D_1 const # 

const arg_Vd_arrangement_sz___4S_0__2D_1

arg_Vm_22_1__S_0__D_1 const # 

const arg_Vm_22_1__S_0__D_1

arg_Vm_22_2__B_0__H_1__S_2__D_3 const # 

const arg_Vm_22_2__B_0__H_1__S_2__D_3

arg_Vm_22_2__D_3 const # 

const arg_Vm_22_2__D_3

arg_Vm_22_2__H_1__S_2 const # 

const arg_Vm_22_2__H_1__S_2

arg_Vm_arrangement_4S const # 

const arg_Vm_arrangement_4S

arg_Vm_arrangement_Q___8B_0__16B_1 const # 

const arg_Vm_arrangement_Q___8B_0__16B_1

arg_Vm_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21 const # 

const arg_Vm_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21

arg_Vm_arrangement_size_Q___8B_00__16B_01 const # 

const arg_Vm_arrangement_size_Q___8B_00__16B_01

arg_Vm_arrangement_size_Q___8B_00__16B_01__1D_30__2D_31 const # 

const arg_Vm_arrangement_size_Q___8B_00__16B_01__1D_30__2D_31

arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21 const # 

const arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21

arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31 const # 

const arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31

arg_Vm_arrangement_size___8H_0__4S_1__2D_2 const # 

const arg_Vm_arrangement_size___8H_0__4S_1__2D_2

arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1 const # 

const arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1

arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11 const # 

const arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11

arg_Vm_arrangement_sz___S_0__D_1_index__sz_L_H__HL_00__H_10_1 const # 

const arg_Vm_arrangement_sz___S_0__D_1_index__sz_L_H__HL_00__H_10_1

arg_Vn_19_4__B_1__H_2__S_4__D_8 const # 

const arg_Vn_19_4__B_1__H_2__S_4__D_8

arg_Vn_19_4__D_8 const # 

const arg_Vn_19_4__D_8

arg_Vn_19_4__H_1__S_2__D_4 const # 

const arg_Vn_19_4__H_1__S_2__D_4

arg_Vn_19_4__S_4__D_8 const # 

const arg_Vn_19_4__S_4__D_8

arg_Vn_1_arrangement_16B const # 

const arg_Vn_1_arrangement_16B

arg_Vn_22_1__D_1 const # 

const arg_Vn_22_1__D_1

arg_Vn_22_1__S_0__D_1 const # 

const arg_Vn_22_1__S_0__D_1

arg_Vn_22_2__B_0__H_1__S_2__D_3 const # 

const arg_Vn_22_2__B_0__H_1__S_2__D_3

arg_Vn_22_2__D_3 const # 

const arg_Vn_22_2__D_3

arg_Vn_22_2__H_0__S_1__D_2 const # 

const arg_Vn_22_2__H_0__S_1__D_2

arg_Vn_22_2__H_1__S_2 const # 

const arg_Vn_22_2__H_1__S_2

arg_Vn_2_arrangement_16B const # 

const arg_Vn_2_arrangement_16B

arg_Vn_3_arrangement_16B const # 

const arg_Vn_3_arrangement_16B

arg_Vn_4_arrangement_16B const # 

const arg_Vn_4_arrangement_16B

arg_Vn_arrangement_16B const # 

const arg_Vn_arrangement_16B

arg_Vn_arrangement_4S const # 

const arg_Vn_arrangement_4S

arg_Vn_arrangement_D_index__1 const # 

const arg_Vn_arrangement_D_index__1

arg_Vn_arrangement_D_index__imm5_1 const # 

const arg_Vn_arrangement_D_index__imm5_1

arg_Vn_arrangement_Q___8B_0__16B_1 const # 

const arg_Vn_arrangement_Q___8B_0__16B_1

arg_Vn_arrangement_Q_sz___2S_00__4S_10__2D_11 const # 

const arg_Vn_arrangement_Q_sz___2S_00__4S_10__2D_11

arg_Vn_arrangement_Q_sz___4S_10 const # 

const arg_Vn_arrangement_Q_sz___4S_10

arg_Vn_arrangement_S_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4_1 const # 

const arg_Vn_arrangement_S_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4_1

arg_Vn_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4__imm5lt4gt_8_1 const # 

const arg_Vn_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4__imm5lt4gt_8_1

arg_Vn_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5_imm4__imm4lt30gt_1__imm4lt31gt_2__imm4lt32gt_4__imm4lt3gt_8_1 const # 

const arg_Vn_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5_imm4__imm4lt30gt_1__imm4lt31gt_2__imm4lt32gt_4__imm4lt3gt_8_1

arg_Vn_arrangement_imm5___B_1__H_2__S_4_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4_1 const # 

const arg_Vn_arrangement_imm5___B_1__H_2__S_4_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4_1

arg_Vn_arrangement_imm5___B_1__H_2_index__imm5__imm5lt41gt_1__imm5lt42gt_2_1 const # 

const arg_Vn_arrangement_imm5___B_1__H_2_index__imm5__imm5lt41gt_1__imm5lt42gt_2_1

arg_Vn_arrangement_imm5___D_8_index__imm5_1 const # 

const arg_Vn_arrangement_imm5___D_8_index__imm5_1

arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__2S_40__4S_41__2D_81 const # 

const arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__2S_40__4S_41__2D_81

arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41 const # 

const arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41

arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81 const # 

const arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81

arg_Vn_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4 const # 

const arg_Vn_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4

arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21 const # 

const arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21

arg_Vn_arrangement_size_Q___8B_00__16B_01 const # 

const arg_Vn_arrangement_size_Q___8B_00__16B_01

arg_Vn_arrangement_size_Q___8B_00__16B_01__1D_30__2D_31 const # 

const arg_Vn_arrangement_size_Q___8B_00__16B_01__1D_30__2D_31

arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11 const # 

const arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11

arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21 const # 

const arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21

arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31 const # 

const arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31

arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__4S_21 const # 

const arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__4S_21

arg_Vn_arrangement_size___2D_3 const # 

const arg_Vn_arrangement_size___2D_3

arg_Vn_arrangement_size___8H_0__4S_1__2D_2 const # 

const arg_Vn_arrangement_size___8H_0__4S_1__2D_2

arg_Vn_arrangement_sz_Q___2S_00__4S_01 const # 

const arg_Vn_arrangement_sz_Q___2S_00__4S_01

arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11 const # 

const arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11

arg_Vn_arrangement_sz_Q___4H_00__8H_01__2S_10__4S_11 const # 

const arg_Vn_arrangement_sz_Q___4H_00__8H_01__2S_10__4S_11

arg_Vn_arrangement_sz___2D_1 const # 

const arg_Vn_arrangement_sz___2D_1

arg_Vn_arrangement_sz___2S_0__2D_1 const # 

const arg_Vn_arrangement_sz___2S_0__2D_1

arg_Vn_arrangement_sz___4S_0__2D_1 const # 

const arg_Vn_arrangement_sz___4S_0__2D_1

arg_Vt_1_arrangement_B_index__Q_S_size_1 const # 

const arg_Vt_1_arrangement_B_index__Q_S_size_1

arg_Vt_1_arrangement_D_index__Q_1 const # 

const arg_Vt_1_arrangement_D_index__Q_1

arg_Vt_1_arrangement_H_index__Q_S_size_1 const # 

const arg_Vt_1_arrangement_H_index__Q_S_size_1

arg_Vt_1_arrangement_S_index__Q_S_1 const # 

const arg_Vt_1_arrangement_S_index__Q_S_1

arg_Vt_1_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31 const # 

const arg_Vt_1_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31

arg_Vt_2_arrangement_B_index__Q_S_size_1 const # 

const arg_Vt_2_arrangement_B_index__Q_S_size_1

arg_Vt_2_arrangement_D_index__Q_1 const # 

const arg_Vt_2_arrangement_D_index__Q_1

arg_Vt_2_arrangement_H_index__Q_S_size_1 const # 

const arg_Vt_2_arrangement_H_index__Q_S_size_1

arg_Vt_2_arrangement_S_index__Q_S_1 const # 

const arg_Vt_2_arrangement_S_index__Q_S_1

arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31 const # 

const arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31

arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31 const # 

const arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31

arg_Vt_3_arrangement_B_index__Q_S_size_1 const # 

const arg_Vt_3_arrangement_B_index__Q_S_size_1

arg_Vt_3_arrangement_D_index__Q_1 const # 

const arg_Vt_3_arrangement_D_index__Q_1

arg_Vt_3_arrangement_H_index__Q_S_size_1 const # 

const arg_Vt_3_arrangement_H_index__Q_S_size_1

arg_Vt_3_arrangement_S_index__Q_S_1 const # 

const arg_Vt_3_arrangement_S_index__Q_S_1

arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31 const # 

const arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31

arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31 const # 

const arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31

arg_Vt_4_arrangement_B_index__Q_S_size_1 const # 

const arg_Vt_4_arrangement_B_index__Q_S_size_1

arg_Vt_4_arrangement_D_index__Q_1 const # 

const arg_Vt_4_arrangement_D_index__Q_1

arg_Vt_4_arrangement_H_index__Q_S_size_1 const # 

const arg_Vt_4_arrangement_H_index__Q_S_size_1

arg_Vt_4_arrangement_S_index__Q_S_1 const # 

const arg_Vt_4_arrangement_S_index__Q_S_1

arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31 const # 

const arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31

arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31 const # 

const arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31

arg_Wa const # 

const arg_Wa

arg_Wd const # 

const arg_Wd

arg_Wds const # 

const arg_Wds

arg_Wm const # 

const arg_Wm

arg_Wm_extend__UXTB_0__UXTH_1__LSL_UXTW_2__UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4 const # 

const arg_Wm_extend__UXTB_0__UXTH_1__LSL_UXTW_2__UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4

arg_Wm_shift__LSL_0__LSR_1__ASR_2__0_31 const # 

const arg_Wm_shift__LSL_0__LSR_1__ASR_2__0_31

arg_Wm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_31 const # 

const arg_Wm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_31

arg_Wn const # 

const arg_Wn

arg_Wns const # 

const arg_Wns

arg_Ws const # 

const arg_Ws

arg_Wt const # 

const arg_Wt

arg_Wt2 const # 

const arg_Wt2

arg_Xa const # 

const arg_Xa

arg_Xd const # 

const arg_Xd

arg_Xds const # 

const arg_Xds

arg_Xm const # 

const arg_Xm

arg_Xm_shift__LSL_0__LSR_1__ASR_2__0_63 const # 

const arg_Xm_shift__LSL_0__LSR_1__ASR_2__0_63

arg_Xm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_63 const # 

const arg_Xm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_63

arg_Xn const # 

const arg_Xn

arg_Xns const # 

const arg_Xns

arg_Xns_mem const # 

const arg_Xns_mem

arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__1_1 const # 

const arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__1_1

arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__2_1 const # 

const arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__2_1

arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__3_1 const # 

const arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__3_1

arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__4_1 const # 

const arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__4_1

arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__absent_0__0_1 const # 

const arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__absent_0__0_1

arg_Xns_mem_offset const # 

const arg_Xns_mem_offset

arg_Xns_mem_optional_imm12_16_unsigned const # 

const arg_Xns_mem_optional_imm12_16_unsigned

arg_Xns_mem_optional_imm12_1_unsigned const # 

const arg_Xns_mem_optional_imm12_1_unsigned

arg_Xns_mem_optional_imm12_2_unsigned const # 

const arg_Xns_mem_optional_imm12_2_unsigned

arg_Xns_mem_optional_imm12_4_unsigned const # 

const arg_Xns_mem_optional_imm12_4_unsigned

arg_Xns_mem_optional_imm12_8_unsigned const # 

const arg_Xns_mem_optional_imm12_8_unsigned

arg_Xns_mem_optional_imm7_16_signed const # 

const arg_Xns_mem_optional_imm7_16_signed

arg_Xns_mem_optional_imm7_4_signed const # 

const arg_Xns_mem_optional_imm7_4_signed

arg_Xns_mem_optional_imm7_8_signed const # 

const arg_Xns_mem_optional_imm7_8_signed

arg_Xns_mem_optional_imm9_1_signed const # 

const arg_Xns_mem_optional_imm9_1_signed

arg_Xns_mem_post_Q__16_0__32_1 const # 

const arg_Xns_mem_post_Q__16_0__32_1

arg_Xns_mem_post_Q__24_0__48_1 const # 

const arg_Xns_mem_post_Q__24_0__48_1

arg_Xns_mem_post_Q__32_0__64_1 const # 

const arg_Xns_mem_post_Q__32_0__64_1

arg_Xns_mem_post_Q__8_0__16_1 const # 

const arg_Xns_mem_post_Q__8_0__16_1

arg_Xns_mem_post_Xm const # 

const arg_Xns_mem_post_Xm

arg_Xns_mem_post_fixedimm_1 const # 

const arg_Xns_mem_post_fixedimm_1

arg_Xns_mem_post_fixedimm_12 const # 

const arg_Xns_mem_post_fixedimm_12

arg_Xns_mem_post_fixedimm_16 const # 

const arg_Xns_mem_post_fixedimm_16

arg_Xns_mem_post_fixedimm_2 const # 

const arg_Xns_mem_post_fixedimm_2

arg_Xns_mem_post_fixedimm_24 const # 

const arg_Xns_mem_post_fixedimm_24

arg_Xns_mem_post_fixedimm_3 const # 

const arg_Xns_mem_post_fixedimm_3

arg_Xns_mem_post_fixedimm_32 const # 

const arg_Xns_mem_post_fixedimm_32

arg_Xns_mem_post_fixedimm_4 const # 

const arg_Xns_mem_post_fixedimm_4

arg_Xns_mem_post_fixedimm_6 const # 

const arg_Xns_mem_post_fixedimm_6

arg_Xns_mem_post_fixedimm_8 const # 

const arg_Xns_mem_post_fixedimm_8

arg_Xns_mem_post_imm7_16_signed const # 

const arg_Xns_mem_post_imm7_16_signed

arg_Xns_mem_post_imm7_4_signed const # 

const arg_Xns_mem_post_imm7_4_signed

arg_Xns_mem_post_imm7_8_signed const # 

const arg_Xns_mem_post_imm7_8_signed

arg_Xns_mem_post_imm9_1_signed const # 

const arg_Xns_mem_post_imm9_1_signed

arg_Xns_mem_post_size__1_0__2_1__4_2__8_3 const # 

const arg_Xns_mem_post_size__1_0__2_1__4_2__8_3

arg_Xns_mem_post_size__2_0__4_1__8_2__16_3 const # 

const arg_Xns_mem_post_size__2_0__4_1__8_2__16_3

arg_Xns_mem_post_size__3_0__6_1__12_2__24_3 const # 

const arg_Xns_mem_post_size__3_0__6_1__12_2__24_3

arg_Xns_mem_post_size__4_0__8_1__16_2__32_3 const # 

const arg_Xns_mem_post_size__4_0__8_1__16_2__32_3

arg_Xns_mem_wb_imm7_16_signed const # 

const arg_Xns_mem_wb_imm7_16_signed

arg_Xns_mem_wb_imm7_4_signed const # 

const arg_Xns_mem_wb_imm7_4_signed

arg_Xns_mem_wb_imm7_8_signed const # 

const arg_Xns_mem_wb_imm7_8_signed

arg_Xns_mem_wb_imm9_1_signed const # 

const arg_Xns_mem_wb_imm9_1_signed

arg_Xs const # 

const arg_Xs

arg_Xt const # 

const arg_Xt

arg_Xt2 const # 

const arg_Xt2

arg_cond_AllowALNV_Normal const # 

const arg_cond_AllowALNV_Normal

arg_cond_NotAllowALNV_Invert const # 

const arg_cond_NotAllowALNV_Invert

arg_conditional const # 

const arg_conditional

arg_immediate_0_127_CRm_op2 const # 

const arg_immediate_0_127_CRm_op2

arg_immediate_0_15_CRm const # 

const arg_immediate_0_15_CRm

arg_immediate_0_15_nzcv const # 

const arg_immediate_0_15_nzcv

arg_immediate_0_31_imm5 const # 

const arg_immediate_0_31_imm5

arg_immediate_0_31_immr const # 

const arg_immediate_0_31_immr

arg_immediate_0_31_imms const # 

const arg_immediate_0_31_imms

arg_immediate_0_63_b5_b40 const # 

const arg_immediate_0_63_b5_b40

arg_immediate_0_63_immh_immb__UIntimmhimmb64_8 const # 

const arg_immediate_0_63_immh_immb__UIntimmhimmb64_8

arg_immediate_0_63_immr const # 

const arg_immediate_0_63_immr

arg_immediate_0_63_imms const # 

const arg_immediate_0_63_imms

arg_immediate_0_65535_imm16 const # 

const arg_immediate_0_65535_imm16

arg_immediate_0_7_op1 const # 

const arg_immediate_0_7_op1

arg_immediate_0_7_op2 const # 

const arg_immediate_0_7_op2

arg_immediate_0_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4 const # 

const arg_immediate_0_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4

arg_immediate_0_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4__UIntimmhimmb64_8 const # 

const arg_immediate_0_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4__UIntimmhimmb64_8

arg_immediate_0_width_m1_immh_immb__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4__UIntimmhimmb64_8 const # 

const arg_immediate_0_width_m1_immh_immb__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4__UIntimmhimmb64_8

arg_immediate_0_width_size__8_0__16_1__32_2 const # 

const arg_immediate_0_width_size__8_0__16_1__32_2

arg_immediate_1_64_immh_immb__128UIntimmhimmb_8 const # 

const arg_immediate_1_64_immh_immb__128UIntimmhimmb_8

arg_immediate_1_width_immh_immb__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4 const # 

const arg_immediate_1_width_immh_immb__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4

arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4 const # 

const arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4

arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4__128UIntimmhimmb_8 const # 

const arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4__128UIntimmhimmb_8

arg_immediate_8x8_a_b_c_d_e_f_g_h const # 

const arg_immediate_8x8_a_b_c_d_e_f_g_h

arg_immediate_ASR_SBFM_32M_bitfield_0_31_immr const # 

const arg_immediate_ASR_SBFM_32M_bitfield_0_31_immr

arg_immediate_ASR_SBFM_64M_bitfield_0_63_immr const # 

const arg_immediate_ASR_SBFM_64M_bitfield_0_63_immr

arg_immediate_BFI_BFM_32M_bitfield_lsb_32_immr const # 

const arg_immediate_BFI_BFM_32M_bitfield_lsb_32_immr

arg_immediate_BFI_BFM_32M_bitfield_width_32_imms const # 

const arg_immediate_BFI_BFM_32M_bitfield_width_32_imms

arg_immediate_BFI_BFM_64M_bitfield_lsb_64_immr const # 

const arg_immediate_BFI_BFM_64M_bitfield_lsb_64_immr

arg_immediate_BFI_BFM_64M_bitfield_width_64_imms const # 

const arg_immediate_BFI_BFM_64M_bitfield_width_64_imms

arg_immediate_BFXIL_BFM_32M_bitfield_lsb_32_immr const # 

const arg_immediate_BFXIL_BFM_32M_bitfield_lsb_32_immr

arg_immediate_BFXIL_BFM_32M_bitfield_width_32_imms const # 

const arg_immediate_BFXIL_BFM_32M_bitfield_width_32_imms

arg_immediate_BFXIL_BFM_64M_bitfield_lsb_64_immr const # 

const arg_immediate_BFXIL_BFM_64M_bitfield_lsb_64_immr

arg_immediate_BFXIL_BFM_64M_bitfield_width_64_imms const # 

const arg_immediate_BFXIL_BFM_64M_bitfield_width_64_imms

arg_immediate_LSL_UBFM_32M_bitfield_0_31_immr const # 

const arg_immediate_LSL_UBFM_32M_bitfield_0_31_immr

arg_immediate_LSL_UBFM_64M_bitfield_0_63_immr const # 

const arg_immediate_LSL_UBFM_64M_bitfield_0_63_immr

arg_immediate_LSR_UBFM_32M_bitfield_0_31_immr const # 

const arg_immediate_LSR_UBFM_32M_bitfield_0_31_immr

arg_immediate_LSR_UBFM_64M_bitfield_0_63_immr const # 

const arg_immediate_LSR_UBFM_64M_bitfield_0_63_immr

arg_immediate_MSL__a_b_c_d_e_f_g_h_cmode__8_0__16_1 const # 

const arg_immediate_MSL__a_b_c_d_e_f_g_h_cmode__8_0__16_1

arg_immediate_OptLSLZero__a_b_c_d_e_f_g_h const # 

const arg_immediate_OptLSLZero__a_b_c_d_e_f_g_h

arg_immediate_OptLSL__a_b_c_d_e_f_g_h_cmode__0_0__8_1 const # 

const arg_immediate_OptLSL__a_b_c_d_e_f_g_h_cmode__0_0__8_1

arg_immediate_OptLSL__a_b_c_d_e_f_g_h_cmode__0_0__8_1__16_2__24_3 const # 

const arg_immediate_OptLSL__a_b_c_d_e_f_g_h_cmode__0_0__8_1__16_2__24_3

arg_immediate_OptLSL_amount_16_0_16 const # 

const arg_immediate_OptLSL_amount_16_0_16

arg_immediate_OptLSL_amount_16_0_48 const # 

const arg_immediate_OptLSL_amount_16_0_48

arg_immediate_SBFIZ_SBFM_32M_bitfield_lsb_32_immr const # 

const arg_immediate_SBFIZ_SBFM_32M_bitfield_lsb_32_immr

arg_immediate_SBFIZ_SBFM_32M_bitfield_width_32_imms const # 

const arg_immediate_SBFIZ_SBFM_32M_bitfield_width_32_imms

arg_immediate_SBFIZ_SBFM_64M_bitfield_lsb_64_immr const # 

const arg_immediate_SBFIZ_SBFM_64M_bitfield_lsb_64_immr

arg_immediate_SBFIZ_SBFM_64M_bitfield_width_64_imms const # 

const arg_immediate_SBFIZ_SBFM_64M_bitfield_width_64_imms

arg_immediate_SBFX_SBFM_32M_bitfield_lsb_32_immr const # 

const arg_immediate_SBFX_SBFM_32M_bitfield_lsb_32_immr

arg_immediate_SBFX_SBFM_32M_bitfield_width_32_imms const # 

const arg_immediate_SBFX_SBFM_32M_bitfield_width_32_imms

arg_immediate_SBFX_SBFM_64M_bitfield_lsb_64_immr const # 

const arg_immediate_SBFX_SBFM_64M_bitfield_lsb_64_immr

arg_immediate_SBFX_SBFM_64M_bitfield_width_64_imms const # 

const arg_immediate_SBFX_SBFM_64M_bitfield_width_64_imms

arg_immediate_UBFIZ_UBFM_32M_bitfield_lsb_32_immr const # 

const arg_immediate_UBFIZ_UBFM_32M_bitfield_lsb_32_immr

arg_immediate_UBFIZ_UBFM_32M_bitfield_width_32_imms const # 

const arg_immediate_UBFIZ_UBFM_32M_bitfield_width_32_imms

arg_immediate_UBFIZ_UBFM_64M_bitfield_lsb_64_immr const # 

const arg_immediate_UBFIZ_UBFM_64M_bitfield_lsb_64_immr

arg_immediate_UBFIZ_UBFM_64M_bitfield_width_64_imms const # 

const arg_immediate_UBFIZ_UBFM_64M_bitfield_width_64_imms

arg_immediate_UBFX_UBFM_32M_bitfield_lsb_32_immr const # 

const arg_immediate_UBFX_UBFM_32M_bitfield_lsb_32_immr

arg_immediate_UBFX_UBFM_32M_bitfield_width_32_imms const # 

const arg_immediate_UBFX_UBFM_32M_bitfield_width_32_imms

arg_immediate_UBFX_UBFM_64M_bitfield_lsb_64_immr const # 

const arg_immediate_UBFX_UBFM_64M_bitfield_lsb_64_immr

arg_immediate_UBFX_UBFM_64M_bitfield_width_64_imms const # 

const arg_immediate_UBFX_UBFM_64M_bitfield_width_64_imms

arg_immediate_bitmask_32_imms_immr const # 

const arg_immediate_bitmask_32_imms_immr

arg_immediate_bitmask_64_N_imms_immr const # 

const arg_immediate_bitmask_64_N_imms_immr

arg_immediate_exp_3_pre_4_a_b_c_d_e_f_g_h const # 

const arg_immediate_exp_3_pre_4_a_b_c_d_e_f_g_h

arg_immediate_exp_3_pre_4_imm8 const # 

const arg_immediate_exp_3_pre_4_imm8

arg_immediate_fbits_min_1_max_0_sub_0_immh_immb__64UIntimmhimmb_4__128UIntimmhimmb_8 const # 

const arg_immediate_fbits_min_1_max_0_sub_0_immh_immb__64UIntimmhimmb_4__128UIntimmhimmb_8

arg_immediate_fbits_min_1_max_0_sub_0_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__64UIntimmhimmb_4__128UIntimmhimmb_8 const # 

const arg_immediate_fbits_min_1_max_0_sub_0_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__64UIntimmhimmb_4__128UIntimmhimmb_8

arg_immediate_fbits_min_1_max_32_sub_64_scale const # 

const arg_immediate_fbits_min_1_max_32_sub_64_scale

arg_immediate_fbits_min_1_max_64_sub_64_scale const # 

const arg_immediate_fbits_min_1_max_64_sub_64_scale

arg_immediate_floatzero const # 

const arg_immediate_floatzero

arg_immediate_index_Q_imm4__imm4lt20gt_00__imm4_10 const # 

const arg_immediate_index_Q_imm4__imm4lt20gt_00__imm4_10

arg_immediate_optional_0_15_CRm const # 

const arg_immediate_optional_0_15_CRm

arg_immediate_optional_0_65535_imm16 const # 

const arg_immediate_optional_0_65535_imm16

arg_immediate_shift_32_implicit_imm16_hw const # 

const arg_immediate_shift_32_implicit_imm16_hw

arg_immediate_shift_32_implicit_inverse_imm16_hw const # 

const arg_immediate_shift_32_implicit_inverse_imm16_hw

arg_immediate_shift_64_implicit_imm16_hw const # 

const arg_immediate_shift_64_implicit_imm16_hw

arg_immediate_shift_64_implicit_inverse_imm16_hw const # 

const arg_immediate_shift_64_implicit_inverse_imm16_hw

arg_immediate_zero const # 

const arg_immediate_zero

arg_option_DMB_BO_system_CRm const # 

const arg_option_DMB_BO_system_CRm

arg_option_DSB_BO_system_CRm const # 

const arg_option_DSB_BO_system_CRm

arg_option_ISB_BI_system_CRm const # 

const arg_option_ISB_BI_system_CRm

arg_prfop_Rt const # 

const arg_prfop_Rt

arg_pstatefield_op1_op2__SPSel_05__DAIFSet_36__DAIFClr_37 const # 

const arg_pstatefield_op1_op2__SPSel_05__DAIFSet_36__DAIFClr_37

arg_slabel_imm14_2 const # 

const arg_slabel_imm14_2

arg_slabel_imm19_2 const # 

const arg_slabel_imm19_2

arg_slabel_imm26_2 const # 

const arg_slabel_imm26_2

arg_slabel_immhi_immlo_0 const # 

const arg_slabel_immhi_immlo_0

arg_slabel_immhi_immlo_12 const # 

const arg_slabel_immhi_immlo_12

arg_sysop_AT_SYS_CR_system const # 

const arg_sysop_AT_SYS_CR_system

arg_sysop_DC_SYS_CR_system const # 

const arg_sysop_DC_SYS_CR_system

arg_sysop_IC_SYS_CR_system const # 

const arg_sysop_IC_SYS_CR_system

arg_sysop_SYS_CR_system const # 

const arg_sysop_SYS_CR_system

arg_sysop_TLBI_SYS_CR_system const # 

const arg_sysop_TLBI_SYS_CR_system

arg_sysreg_o0_op1_CRn_CRm_op2 const # 

const arg_sysreg_o0_op1_CRn_CRm_op2

asr const # 

const asr

decoderCover var # 

var decoderCover []bool

errShort var # 

var errShort = *ast.CallExpr

errUnknown var # 

var errUnknown = *ast.CallExpr

fOpsWithoutFPrefix var #

floating point instructions without "F" prefix.

var fOpsWithoutFPrefix = map[Op]bool{...}

instFormats var # 

var instFormats = [...]instFormat{...}

lsl const # 

const lsl

lsr const # 

const lsr

noSuffixOpSet var #

No need add "W" to opcode suffix. Opcode must be inserted in ascending order.

var noSuffixOpSet = *ast.CallExpr

opstr var # 

var opstr = [...]string{...}

ror const # 

const ror

sxtb const # 

const sxtb

sxth const # 

const sxth

sxtw const # 

const sxtw

sxtx const # 

const sxtx

sysInstsAttrs var # 

var sysInstsAttrs = map[sysInstFields]sysInstAttrs{...}

sys_AT const # 

const sys_AT sys = iota

sys_DC const # 

const sys_DC

sys_IC const # 

const sys_IC

sys_SYS const # 

const sys_SYS

sys_TLBI const # 

const sys_TLBI

uxtb const # 

const uxtb

uxth const # 

const uxth

uxtw const # 

const uxtw

uxtx const # 

const uxtx

Type Aliases

AddrMode type #

An AddrMode is an ARM addressing mode.

type AddrMode uint8

Args type #

An Args holds the instruction arguments. If an instruction has fewer than 5 arguments, the final elements in the array are nil.

type Args [5]Arg

Arrangement type # 

type Arrangement uint8

ExtShift type # 

type ExtShift uint8

Imm_c type #

An Imm_c is an integer constant for SYS/SYSL/TLBI instruction.

type Imm_c uint8

Imm_clrex type #

An Imm_clrex is an integer constant for CLREX instruction.

type Imm_clrex uint8

Imm_dcps type #

An Imm_dcps is an integer constant for DCPS[123] instruction.

type Imm_dcps uint16

Imm_hint type #

An Imm_hint is an integer constant for HINT instruction.

type Imm_hint uint8

Imm_option type #

An Imm_option is an integer constant for DMB/DSB/ISB instruction.

type Imm_option uint8

Imm_prfop type #

An Imm_prfop is an integer constant for PRFM instruction.

type Imm_prfop uint8

Op type #

An Op is an ARM64 opcode.

type Op uint16

PCRel type #

A PCRel describes a memory address (usually a code label) as a distance relative to the program counter.

type PCRel int64

Pstatefield type # 

type Pstatefield uint8

Reg type #

A Reg is a single register. The zero value denotes W0, not the absence of a register.

type Reg uint16

RegSP type #

A RegSP represent a register and X31/W31 is regarded as SP/WSP.

type RegSP Reg

instArg type # 

type instArg uint16

instArgs type # 

type instArgs [5]instArg

sys type # 

type sys uint8

Interfaces

Arg interface #

An Arg is a single instruction argument, one of these types: Reg, RegSP, ImmShift, RegExtshiftAmount, PCRel, MemImmediate, MemExtend, Imm, Imm64, Imm_hint, Imm_clrex, Imm_dcps, Cond, Imm_c, Imm_option, Imm_prfop, Pstatefield, Systemreg, Imm_fp RegisterWithArrangement, RegisterWithArrangementAndIndex.

type Arg interface {
isArg()
String() string
}

Structs

Cond struct #

Standard conditions.

type Cond struct {
Value uint8
Invert bool
}

Imm struct #

An Imm is an integer constant.

type Imm struct {
Imm uint32
Decimal bool
}

Imm64 struct # 

type Imm64 struct {
Imm uint64
Decimal bool
}

ImmShift struct # 

type ImmShift struct {
imm uint16
shift uint8
}

Imm_fp struct #

An Imm_fp is a signed floating-point constant.

type Imm_fp struct {
s uint8
exp int8
pre uint8
}

Inst struct #

An Inst is a single instruction.

type Inst struct {
Op Op
Enc uint32
Args Args
}

MemExtend struct #

A MemExtend is a memory reference made up of a base R and index expression X. The effective memory address is R or R+X depending on Index, Extend and Amount.

type MemExtend struct {
Base RegSP
Index Reg
Extend ExtShift
Amount uint8
ShiftMustBeZero bool
}

MemImmediate struct #

A MemImmediate is a memory reference made up of a base R and immediate X. The effective memory address is R or R+X depending on AddrMode.

type MemImmediate struct {
Base RegSP
Mode AddrMode
imm int32
}

RegExtshiftAmount struct # 

type RegExtshiftAmount struct {
reg Reg
extShift ExtShift
amount uint8
show_zero bool
}

RegisterWithArrangement struct #

Register with arrangement: ., { .8B, .8B},

type RegisterWithArrangement struct {
r Reg
a Arrangement
cnt uint8
}

RegisterWithArrangementAndIndex struct #

Register with arrangement and index: .[], { .B, .B }[].

type RegisterWithArrangementAndIndex struct {
r Reg
a Arrangement
index uint8
cnt uint8
}

Systemreg struct # 

type Systemreg struct {
op0 uint8
op1 uint8
cn uint8
cm uint8
op2 uint8
}

instFormat struct #

An instFormat describes the format of an instruction encoding. An instruction with 32-bit value x matches the format if x&mask == value and the predicator: canDecode(x) return true.

type instFormat struct {
mask uint32
value uint32
op Op
args instArgs
canDecode func(instr uint32) bool
}

sysInstAttrs struct # 

type sysInstAttrs struct {
typ sys
name string
hasOperand2 bool
}

sysInstFields struct # 

type sysInstFields struct {
op1 uint8
cn uint8
cm uint8
op2 uint8
}

sysOp struct # 

type sysOp struct {
op sysInstFields
r Reg
hasOperand2 bool
}

Functions

Decode function #

Decode decodes the 4 bytes in src as a single instruction.

func Decode(src []byte) (inst Inst, err error)

GNUSyntax function #

GNUSyntax returns the GNU assembler syntax for the instruction, as defined by GNU binutils. This form typically matches the syntax defined in the ARM Reference Manual.

func GNUSyntax(inst Inst) string

GoSyntax function #

GoSyntax returns the Go assembler syntax for the instruction. The syntax was originally defined by Plan 9. The pc is the program counter of the instruction, used for expanding PC-relative addresses into absolute ones. The symname function queries the symbol table for the program being disassembled. Given a target address it returns the name and base address of the symbol containing the target, if any; otherwise it returns "", 0. The reader text should read from the text segment using text addresses as offsets; it is used to display pc-relative loads as constant loads.

func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64), text io.ReaderAt) string

String method # 

func (rea RegExtshiftAmount) String() string

String method # 

func (op Op) String() string

String method # 

func (c Cond) String() string

String method # 

func (i Imm_dcps) String() string

String method # 

func (i Imm_prfop) String() string

String method # 

func (i Imm) String() string

String method # 

func (i Imm_clrex) String() string

String method # 

func (p Pstatefield) String() string

String method # 

func (i Imm_hint) String() string

String method # 

func (s Systemreg) String() string

String method # 

func (i Imm64) String() string

String method # 

func (r RegisterWithArrangement) String() string

String method # 

func (i Imm_fp) String() string

String method # 

func (i Imm_c) String() string

String method # 

func (m MemExtend) String() string

String method # 

func (i Imm_option) String() string

String method # 

func (r RegisterWithArrangementAndIndex) String() string

String method # 

func (m MemImmediate) String() string

String method # 

func (i Inst) String() string

String method # 

func (r Reg) String() string

String method # 

func (r RegSP) String() string

String method # 

func (is ImmShift) String() string

String method # 

func (s sysOp) String() string

String method # 

func (extShift ExtShift) String() string

String method # 

func (s sysInstFields) String() string

String method # 

func (a Arrangement) String() (result string)

String method # 

func (r PCRel) String() string

at_sys_cr_system_cond function # 

func at_sys_cr_system_cond(instr uint32) bool

bfi_bfm_32m_bitfield_cond function # 

func bfi_bfm_32m_bitfield_cond(instr uint32) bool

bfi_bfm_64m_bitfield_cond function # 

func bfi_bfm_64m_bitfield_cond(instr uint32) bool

bfxil_bfm_32m_bitfield_cond function # 

func bfxil_bfm_32m_bitfield_cond(instr uint32) bool

bfxil_bfm_64m_bitfield_cond function # 

func bfxil_bfm_64m_bitfield_cond(instr uint32) bool

bfxpreferred_4 function # 

func bfxpreferred_4(sf uint32, opc1 uint32, imms uint32, immr uint32) bool

bit_count function # 

func bit_count(x uint32) uint8

cinc_csinc_32_condsel_cond function # 

func cinc_csinc_32_condsel_cond(instr uint32) bool

cinc_csinc_64_condsel_cond function # 

func cinc_csinc_64_condsel_cond(instr uint32) bool

cinv_csinv_32_condsel_cond function # 

func cinv_csinv_32_condsel_cond(instr uint32) bool

cinv_csinv_64_condsel_cond function # 

func cinv_csinv_64_condsel_cond(instr uint32) bool

cneg_csneg_32_condsel_cond function # 

func cneg_csneg_32_condsel_cond(instr uint32) bool

cneg_csneg_64_condsel_cond function # 

func cneg_csneg_64_condsel_cond(instr uint32) bool

csinc_general_cond function # 

func csinc_general_cond(instr uint32) bool

csinv_general_cond function # 

func csinv_general_cond(instr uint32) bool

dc_sys_cr_system_cond function # 

func dc_sys_cr_system_cond(instr uint32) bool

decodeArg function #

decodeArg decodes the arg described by aop from the instruction bits x. It returns nil if x cannot be decoded according to aop.

func decodeArg(aop instArg, x uint32) Arg

extract_bit function # 

func extract_bit(value uint32, bit uint32) uint32

fcvtzs_asimdshf_c_cond function # 

func fcvtzs_asimdshf_c_cond(instr uint32) bool

fcvtzs_asisdshf_c_cond function # 

func fcvtzs_asisdshf_c_cond(instr uint32) bool

fcvtzu_asimdshf_c_cond function # 

func fcvtzu_asimdshf_c_cond(instr uint32) bool

fcvtzu_asisdshf_c_cond function # 

func fcvtzu_asisdshf_c_cond(instr uint32) bool

getAttrs method # 

func (s sysInstFields) getAttrs() sysInstAttrs

getType method # 

func (s sysInstFields) getType() sys

handle_ExtendedRegister function # 

func handle_ExtendedRegister(x uint32, has_width bool) Arg

handle_ImmediateShiftedRegister function # 

func handle_ImmediateShiftedRegister(x uint32, max uint8, is_w bool, has_ror bool) Arg

handle_MemExtend function # 

func handle_MemExtend(x uint32, mult uint8, absent bool) Arg

handle_bitmasks function # 

func handle_bitmasks(x uint32, datasize uint8) Arg

ic_sys_cr_system_cond function # 

func ic_sys_cr_system_cond(instr uint32) bool

init function # 

func init()

isArg method # 

func (MemImmediate) isArg()

isArg method # 

func (Imm_prfop) isArg()

isArg method # 

func (Imm_hint) isArg()

isArg method # 

func (Imm_fp) isArg()

isArg method # 

func (Imm_option) isArg()

isArg method # 

func (RegisterWithArrangement) isArg()

isArg method # 

func (Imm) isArg()

isArg method # 

func (RegisterWithArrangementAndIndex) isArg()

isArg method # 

func (MemExtend) isArg()

isArg method # 

func (s sysOp) isArg()

isArg method # 

func (Imm_clrex) isArg()

isArg method # 

func (s sysInstFields) isArg()

isArg method # 

func (PCRel) isArg()

isArg method # 

func (Cond) isArg()

isArg method # 

func (RegExtshiftAmount) isArg()

isArg method # 

func (Systemreg) isArg()

isArg method # 

func (Pstatefield) isArg()

isArg method # 

func (ImmShift) isArg()

isArg method # 

func (Imm64) isArg()

isArg method # 

func (RegSP) isArg()

isArg method # 

func (Imm_dcps) isArg()

isArg method # 

func (Reg) isArg()

isArg method # 

func (Imm_c) isArg()

is_ones_n16 function # 

func is_ones_n16(x uint32) bool

is_zero function # 

func is_zero(x uint32) bool

lsl_ubfm_32m_bitfield_cond function # 

func lsl_ubfm_32m_bitfield_cond(instr uint32) bool

lsl_ubfm_64m_bitfield_cond function # 

func lsl_ubfm_64m_bitfield_cond(instr uint32) bool

mov_add_32_addsub_imm_cond function # 

func mov_add_32_addsub_imm_cond(instr uint32) bool

mov_add_64_addsub_imm_cond function # 

func mov_add_64_addsub_imm_cond(instr uint32) bool

mov_movn_32_movewide_cond function # 

func mov_movn_32_movewide_cond(instr uint32) bool

mov_movn_64_movewide_cond function # 

func mov_movn_64_movewide_cond(instr uint32) bool

mov_movz_32_movewide_cond function # 

func mov_movz_32_movewide_cond(instr uint32) bool

mov_movz_64_movewide_cond function # 

func mov_movz_64_movewide_cond(instr uint32) bool

mov_orr_32_log_imm_cond function # 

func mov_orr_32_log_imm_cond(instr uint32) bool

mov_orr_64_log_imm_cond function # 

func mov_orr_64_log_imm_cond(instr uint32) bool

mov_orr_asimdsame_only_cond function # 

func mov_orr_asimdsame_only_cond(instr uint32) bool

mov_umov_asimdins_w_w_cond function # 

func mov_umov_asimdins_w_w_cond(instr uint32) bool

mov_umov_asimdins_x_x_cond function # 

func mov_umov_asimdins_x_x_cond(instr uint32) bool

move_wide_preferred_4 function # 

func move_wide_preferred_4(sf uint32, N uint32, imms uint32, immr uint32) bool

plan9Arg function # 

func plan9Arg(inst *Inst, pc uint64, symname func(uint64) (string, uint64), arg Arg) string

plan9gpr function #

Convert a general-purpose register to plan9 assembly format.

func plan9gpr(r Reg) string

ror_extr_32_extract_cond function # 

func ror_extr_32_extract_cond(instr uint32) bool

ror_extr_64_extract_cond function # 

func ror_extr_64_extract_cond(instr uint32) bool

rshrn_asimdshf_n_cond function # 

func rshrn_asimdshf_n_cond(instr uint32) bool

sbfiz_sbfm_32m_bitfield_cond function # 

func sbfiz_sbfm_32m_bitfield_cond(instr uint32) bool

sbfiz_sbfm_64m_bitfield_cond function # 

func sbfiz_sbfm_64m_bitfield_cond(instr uint32) bool

sbfx_sbfm_32m_bitfield_cond function # 

func sbfx_sbfm_32m_bitfield_cond(instr uint32) bool

sbfx_sbfm_64m_bitfield_cond function # 

func sbfx_sbfm_64m_bitfield_cond(instr uint32) bool

scvtf_asimdshf_c_cond function # 

func scvtf_asimdshf_c_cond(instr uint32) bool

scvtf_asisdshf_c_cond function # 

func scvtf_asisdshf_c_cond(instr uint32) bool

shl_asimdshf_r_cond function # 

func shl_asimdshf_r_cond(instr uint32) bool

shl_asisdshf_r_cond function # 

func shl_asisdshf_r_cond(instr uint32) bool

shrn_asimdshf_n_cond function # 

func shrn_asimdshf_n_cond(instr uint32) bool

sli_asimdshf_r_cond function # 

func sli_asimdshf_r_cond(instr uint32) bool

sli_asisdshf_r_cond function # 

func sli_asisdshf_r_cond(instr uint32) bool

sqrshrn_asimdshf_n_cond function # 

func sqrshrn_asimdshf_n_cond(instr uint32) bool

sqrshrn_asisdshf_n_cond function # 

func sqrshrn_asisdshf_n_cond(instr uint32) bool

sqrshrun_asimdshf_n_cond function # 

func sqrshrun_asimdshf_n_cond(instr uint32) bool

sqrshrun_asisdshf_n_cond function # 

func sqrshrun_asisdshf_n_cond(instr uint32) bool

sqshl_asimdshf_r_cond function # 

func sqshl_asimdshf_r_cond(instr uint32) bool

sqshl_asisdshf_r_cond function # 

func sqshl_asisdshf_r_cond(instr uint32) bool

sqshlu_asimdshf_r_cond function # 

func sqshlu_asimdshf_r_cond(instr uint32) bool

sqshlu_asisdshf_r_cond function # 

func sqshlu_asisdshf_r_cond(instr uint32) bool

sqshrn_asimdshf_n_cond function # 

func sqshrn_asimdshf_n_cond(instr uint32) bool

sqshrn_asisdshf_n_cond function # 

func sqshrn_asisdshf_n_cond(instr uint32) bool

sqshrun_asimdshf_n_cond function # 

func sqshrun_asimdshf_n_cond(instr uint32) bool

sqshrun_asisdshf_n_cond function # 

func sqshrun_asisdshf_n_cond(instr uint32) bool

sri_asimdshf_r_cond function # 

func sri_asimdshf_r_cond(instr uint32) bool

sri_asisdshf_r_cond function # 

func sri_asisdshf_r_cond(instr uint32) bool

srshr_asimdshf_r_cond function # 

func srshr_asimdshf_r_cond(instr uint32) bool

srshr_asisdshf_r_cond function # 

func srshr_asisdshf_r_cond(instr uint32) bool

srsra_asimdshf_r_cond function # 

func srsra_asimdshf_r_cond(instr uint32) bool

srsra_asisdshf_r_cond function # 

func srsra_asisdshf_r_cond(instr uint32) bool

sshll_asimdshf_l_cond function # 

func sshll_asimdshf_l_cond(instr uint32) bool

sshr_asimdshf_r_cond function # 

func sshr_asimdshf_r_cond(instr uint32) bool

sshr_asisdshf_r_cond function # 

func sshr_asisdshf_r_cond(instr uint32) bool

ssra_asimdshf_r_cond function # 

func ssra_asimdshf_r_cond(instr uint32) bool

ssra_asisdshf_r_cond function # 

func ssra_asisdshf_r_cond(instr uint32) bool

sxtl_sshll_asimdshf_l_cond function # 

func sxtl_sshll_asimdshf_l_cond(instr uint32) bool

sys_op_4 function # 

func sys_op_4(op1 uint32, crn uint32, crm uint32, op2 uint32) sys

tlbi_sys_cr_system_cond function # 

func tlbi_sys_cr_system_cond(instr uint32) bool

ubfiz_ubfm_32m_bitfield_cond function # 

func ubfiz_ubfm_32m_bitfield_cond(instr uint32) bool

ubfiz_ubfm_64m_bitfield_cond function # 

func ubfiz_ubfm_64m_bitfield_cond(instr uint32) bool

ubfx_ubfm_32m_bitfield_cond function # 

func ubfx_ubfm_32m_bitfield_cond(instr uint32) bool

ubfx_ubfm_64m_bitfield_cond function # 

func ubfx_ubfm_64m_bitfield_cond(instr uint32) bool

ucvtf_asimdshf_c_cond function # 

func ucvtf_asimdshf_c_cond(instr uint32) bool

ucvtf_asisdshf_c_cond function # 

func ucvtf_asisdshf_c_cond(instr uint32) bool

uqrshrn_asimdshf_n_cond function # 

func uqrshrn_asimdshf_n_cond(instr uint32) bool

uqrshrn_asisdshf_n_cond function # 

func uqrshrn_asisdshf_n_cond(instr uint32) bool

uqshl_asimdshf_r_cond function # 

func uqshl_asimdshf_r_cond(instr uint32) bool

uqshl_asisdshf_r_cond function # 

func uqshl_asisdshf_r_cond(instr uint32) bool

uqshrn_asimdshf_n_cond function # 

func uqshrn_asimdshf_n_cond(instr uint32) bool

uqshrn_asisdshf_n_cond function # 

func uqshrn_asisdshf_n_cond(instr uint32) bool

urshr_asimdshf_r_cond function # 

func urshr_asimdshf_r_cond(instr uint32) bool

urshr_asisdshf_r_cond function # 

func urshr_asisdshf_r_cond(instr uint32) bool

ursra_asimdshf_r_cond function # 

func ursra_asimdshf_r_cond(instr uint32) bool

ursra_asisdshf_r_cond function # 

func ursra_asisdshf_r_cond(instr uint32) bool

ushll_asimdshf_l_cond function # 

func ushll_asimdshf_l_cond(instr uint32) bool

ushr_asimdshf_r_cond function # 

func ushr_asimdshf_r_cond(instr uint32) bool

ushr_asisdshf_r_cond function # 

func ushr_asisdshf_r_cond(instr uint32) bool

usra_asimdshf_r_cond function # 

func usra_asimdshf_r_cond(instr uint32) bool

usra_asisdshf_r_cond function # 

func usra_asisdshf_r_cond(instr uint32) bool

uxtl_ushll_asimdshf_l_cond function # 

func uxtl_ushll_asimdshf_l_cond(instr uint32) bool

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