Imports #
"encoding/binary"
"fmt"
"strings"
"fmt"
"strings"
"fmt"
"strings"
"encoding/binary"
"fmt"
"strings"
"fmt"
"strings"
"fmt"
"strings"
const ADDI_Dconst ADDI_Wconst ADDU16I_Dconst ADD_Dconst ADD_Wconst ALSL_Dconst ALSL_Wconst ALSL_WUconst AMADD_Bconst AMADD_Dconst AMADD_DB_Bconst AMADD_DB_Dconst AMADD_DB_Hconst AMADD_DB_Wconst AMADD_Hconst AMADD_Wconst AMAND_Dconst AMAND_DB_Dconst AMAND_DB_Wconst AMAND_Wconst AMCAS_Bconst AMCAS_Dconst AMCAS_DB_Bconst AMCAS_DB_Dconst AMCAS_DB_Hconst AMCAS_DB_Wconst AMCAS_Hconst AMCAS_Wconst AMMAX_Dconst AMMAX_DB_Dconst AMMAX_DB_DUconst AMMAX_DB_Wconst AMMAX_DB_WUconst AMMAX_DUconst AMMAX_Wconst AMMAX_WUconst AMMIN_Dconst AMMIN_DB_Dconst AMMIN_DB_DUconst AMMIN_DB_Wconst AMMIN_DB_WUconst AMMIN_DUconst AMMIN_Wconst AMMIN_WUconst AMOR_Dconst AMOR_DB_Dconst AMOR_DB_Wconst AMOR_Wconst AMSWAP_Bconst AMSWAP_Dconst AMSWAP_DB_Bconst AMSWAP_DB_Dconst AMSWAP_DB_Hconst AMSWAP_DB_Wconst AMSWAP_Hconst AMSWAP_Wconst AMXOR_Dconst AMXOR_DB_Dconst AMXOR_DB_Wconst AMXOR_Wconst ANDconst ANDIconst ANDNconst ASRTGT_Dconst ASRTLE_Dconst Bconst BCEQZconst BCNEZconst BEQconst BEQZconst BGEconst BGEUconst BITREV_4Bconst BITREV_8Bconst BITREV_Dconst BITREV_Wconst BLconst BLTconst BLTUconst BNEconst BNEZconst BREAKconst BSTRINS_Dconst BSTRINS_Wconst BSTRPICK_Dconst BSTRPICK_Wconst BYTEPICK_Dconst BYTEPICK_Wconst CACOPconst CLO_Dconst CLO_Wconst CLZ_Dconst CLZ_Wconst CPUCFGconst CRCC_W_B_Wconst CRCC_W_D_Wconst CRCC_W_H_Wconst CRCC_W_W_Wconst CRC_W_B_Wconst CRC_W_D_Wconst CRC_W_H_Wconst CRC_W_W_Wconst CSRRDconst CSRWRconst CSRXCHGconst CTO_Dconst CTO_Wconst CTZ_Dconst CTZ_Wconst DBARconst DBCLconst DIV_Dconst DIV_DUconst DIV_Wconst DIV_WUconst ERTNconst EXT_W_Bconst EXT_W_HFloat point register
const F0const F1const F10const F11const F12const F13const F14const F15const F16const F17const F18const F19const F2const F20const F21const F22const F23const F24const F25const F26const F27const F28const F29const F3const F30const F31const F4const F5const F6const F7const F8const F9const FABS_Dconst FABS_Sconst FADD_Dconst FADD_Sconst FCC0 Fcc = iotaconst FCC1const FCC2const FCC3const FCC4const FCC5const FCC6const FCC7const FCLASS_Dconst FCLASS_Sconst FCMP_CAF_Dconst FCMP_CAF_Sconst FCMP_CEQ_Dconst FCMP_CEQ_Sconst FCMP_CLE_Dconst FCMP_CLE_Sconst FCMP_CLT_Dconst FCMP_CLT_Sconst FCMP_CNE_Dconst FCMP_CNE_Sconst FCMP_COR_Dconst FCMP_COR_Sconst FCMP_CUEQ_Dconst FCMP_CUEQ_Sconst FCMP_CULE_Dconst FCMP_CULE_Sconst FCMP_CULT_Dconst FCMP_CULT_Sconst FCMP_CUNE_Dconst FCMP_CUNE_Sconst FCMP_CUN_Dconst FCMP_CUN_Sconst FCMP_SAF_Dconst FCMP_SAF_Sconst FCMP_SEQ_Dconst FCMP_SEQ_Sconst FCMP_SLE_Dconst FCMP_SLE_Sconst FCMP_SLT_Dconst FCMP_SLT_Sconst FCMP_SNE_Dconst FCMP_SNE_Sconst FCMP_SOR_Dconst FCMP_SOR_Sconst FCMP_SUEQ_Dconst FCMP_SUEQ_Sconst FCMP_SULE_Dconst FCMP_SULE_Sconst FCMP_SULT_Dconst FCMP_SULT_Sconst FCMP_SUNE_Dconst FCMP_SUNE_Sconst FCMP_SUN_Dconst FCMP_SUN_Sconst FCOPYSIGN_Dconst FCOPYSIGN_Sconst FCSR0 Fcsr = iotaconst FCSR1const FCSR2const FCSR3const FCVT_D_Sconst FCVT_S_Dconst FDIV_Dconst FDIV_Sconst FFINT_D_Lconst FFINT_D_Wconst FFINT_S_Lconst FFINT_S_Wconst FLDGT_Dconst FLDGT_Sconst FLDLE_Dconst FLDLE_Sconst FLDX_Dconst FLDX_Sconst FLD_Dconst FLD_Sconst FLOGB_Dconst FLOGB_Sconst FMADD_Dconst FMADD_Sconst FMAXA_Dconst FMAXA_Sconst FMAX_Dconst FMAX_Sconst FMINA_Dconst FMINA_Sconst FMIN_Dconst FMIN_Sconst FMOV_Dconst FMOV_Sconst FMSUB_Dconst FMSUB_Sconst FMUL_Dconst FMUL_Sconst FNEG_Dconst FNEG_Sconst FNMADD_Dconst FNMADD_Sconst FNMSUB_Dconst FNMSUB_Sconst FRECIPE_Dconst FRECIPE_Sconst FRECIP_Dconst FRECIP_Sconst FRINT_Dconst FRINT_Sconst FRSQRTE_Dconst FRSQRTE_Sconst FRSQRT_Dconst FRSQRT_Sconst FSCALEB_Dconst FSCALEB_Sconst FSELconst FSQRT_Dconst FSQRT_Sconst FSTGT_Dconst FSTGT_Sconst FSTLE_Dconst FSTLE_Sconst FSTX_Dconst FSTX_Sconst FST_Dconst FST_Sconst FSUB_Dconst FSUB_Sconst FTINTRM_L_Dconst FTINTRM_L_Sconst FTINTRM_W_Dconst FTINTRM_W_Sconst FTINTRNE_L_Dconst FTINTRNE_L_Sconst FTINTRNE_W_Dconst FTINTRNE_W_Sconst FTINTRP_L_Dconst FTINTRP_L_Sconst FTINTRP_W_Dconst FTINTRP_W_Sconst FTINTRZ_L_Dconst FTINTRZ_L_Sconst FTINTRZ_W_Dconst FTINTRZ_W_Sconst FTINT_L_Dconst FTINT_L_Sconst FTINT_W_Dconst FTINT_W_Sconst IBARconst IDLEconst INVTLBconst IOCSRRD_Bconst IOCSRRD_Dconst IOCSRRD_Hconst IOCSRRD_Wconst IOCSRWR_Bconst IOCSRWR_Dconst IOCSRWR_Hconst IOCSRWR_Wconst JIRLconst LDDIRconst LDGT_Bconst LDGT_Dconst LDGT_Hconst LDGT_Wconst LDLE_Bconst LDLE_Dconst LDLE_Hconst LDLE_Wconst LDPTEconst LDPTR_Dconst LDPTR_Wconst LDX_Bconst LDX_BUconst LDX_Dconst LDX_Hconst LDX_HUconst LDX_Wconst LDX_WUconst LD_Bconst LD_BUconst LD_Dconst LD_Hconst LD_HUconst LD_Wconst LD_WUconst LLACQ_Dconst LLACQ_Wconst LL_Dconst LL_Wconst LU12I_Wconst LU32I_Dconst LU52I_Dconst MASKEQZconst MASKNEZconst MOD_Dconst MOD_DUconst MOD_Wconst MOD_WUconst MOVCF2FRconst MOVCF2GRconst MOVFCSR2GRconst MOVFR2CFconst MOVFR2GR_Dconst MOVFR2GR_Sconst MOVFRH2GR_Sconst MOVGR2CFconst MOVGR2FCSRconst MOVGR2FRH_Wconst MOVGR2FR_Dconst MOVGR2FR_Wconst MULH_Dconst MULH_DUconst MULH_Wconst MULH_WUconst MULW_D_Wconst MULW_D_WUconst MUL_Dconst MUL_Wconst NORconst ORconst ORIconst ORNconst PCADDIconst PCADDU12Iconst PCADDU18Iconst PCALAU12Iconst PRELDconst PRELDXGeneral-purpose register
const R0 Reg = iotaconst R1const R10const R11const R12const R13const R14const R15const R16const R17const R18const R19const R2const R20const R21const R22const R23const R24const R25const R26const R27const R28const R29const R3const R30const R31const R4const R5const R6const R7const R8const R9const RDTIMEH_Wconst RDTIMEL_Wconst RDTIME_Dconst REVB_2Hconst REVB_2Wconst REVB_4Hconst REVB_Dconst REVH_2Wconst REVH_Dconst ROTRI_Dconst ROTRI_Wconst ROTR_Dconst ROTR_Wconst SCREL_Dconst SCREL_Wconst SC_Dconst SC_Qconst SC_Wconst SLLI_Dconst SLLI_Wconst SLL_Dconst SLL_Wconst SLTconst SLTIconst SLTUconst SLTUIconst SRAI_Dconst SRAI_Wconst SRA_Dconst SRA_Wconst SRLI_Dconst SRLI_Wconst SRL_Dconst SRL_Wconst STGT_Bconst STGT_Dconst STGT_Hconst STGT_Wconst STLE_Bconst STLE_Dconst STLE_Hconst STLE_Wconst STPTR_Dconst STPTR_Wconst STX_Bconst STX_Dconst STX_Hconst STX_Wconst ST_Bconst ST_Dconst ST_Hconst ST_Wconst SUB_Dconst SUB_Wconst SYSCALLconst TLBCLRconst TLBFILLconst TLBFLUSHconst TLBRDconst TLBSRCHconst TLBWRconst XORconst XORIconst _ Op = iotaconst _ instArg = iotaconst arg_caconst arg_cdconst arg_cjconst arg_code_14_0const arg_code_4_011-15
const arg_csr_23_10const arg_faconst arg_fcsr_4_0const arg_fcsr_9_51-5
const arg_fdconst arg_fjconst arg_fkconst arg_hint_14_026-30
const arg_hint_4_0const arg_level_14_0const arg_level_17_10const arg_lsbdconst arg_lsbwconst arg_msbdconst arg_msbwconst arg_offset_15_0const arg_offset_20_036~
const arg_offset_25_0const arg_op_4_0const arg_rd6-10
const arg_rjconst arg_rkconst arg_sa2_16_1516-20
const arg_sa3_17_15const arg_seq_17_1031-35
const arg_si12_21_10const arg_si14_23_10const arg_si16_25_10const arg_si20_24_521-25
const arg_ui12_21_10const arg_ui5_14_10const arg_ui6_15_10var decoderCover []boolvar errShort = *ast.CallExprvar errUnknown = *ast.CallExprvar instFormats = [...]instFormat{...}var opstr = [...]string{...}var plan9OpMap = map[Op]string{...}An Args holds the instruction arguments. If an instruction has fewer than 5 arguments, the final elements in the array are nil.
type Args [5]Argtype CodeSimm int16float condition flags register
type Fcc uint8float control status register
type Fcsr uint8An Op is an Loong64 opcode.
type Op uint16A Reg is a single register. The zero value denotes R0, not the absence of a register.
type Reg uint16type SaSimm int16type instArg uint16type instArgs [5]instArgAn Arg is a single instruction argument
type Arg interface {
String() string
}An Inst is a single instruction.
type Inst struct {
Op Op
Enc uint32
Args Args
}type OffsetSimm struct {
Imm int32
Width uint8
}type Simm16 struct {
Imm int16
Width uint8
}type Simm32 struct {
Imm int32
Width uint8
}An Imm is an integer constant.
type Uimm struct {
Imm uint32
Decimal bool
}An instFormat describes the format of an instruction encoding.
type instFormat struct {
mask uint32
value uint32
op Op
args instArgs
}Decode decodes the 4 bytes in src as a single instruction.
func Decode(src []byte) (inst Inst, err error)GNUSyntax returns the GNU assembler syntax for the instruction, as defined by GNU binutils. This form typically matches the syntax defined in the Loong64 Reference Manual. See https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html
func GNUSyntax(inst Inst) stringGoSyntax returns the Go assembler syntax for the instruction. The syntax was originally defined by Plan 9. The pc is the program counter of the instruction, used for expanding PC-relative addresses into absolute ones. The symname function queries the symbol table for the program being disassembled. Given a target address it returns the name and base address of the symbol containing the target, if any; otherwise it returns "", 0.
func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64)) stringfunc (f Fcc) String() stringfunc (si Simm16) String() stringNOTE: The actual Op values are defined in tables.go. They are chosen to simplify instruction decoding and are not a dense packing from 0 to N, although the density is high, probably at least 90%.
func (op Op) String() stringfunc (r Reg) String() stringfunc (f Fcsr) String() stringfunc (c CodeSimm) String() stringfunc (i Uimm) String() stringfunc (i Inst) String() stringfunc (si Simm32) String() stringfunc (o OffsetSimm) String() stringfunc (s SaSimm) String() stringdecodeArg decodes the arg described by aop from the instruction bits x. It returns nil if x cannot be decoded according to aop.
func decodeArg(aop instArg, x uint32, index int) Argfunc init()func offsConvInt32(imm int32, width uint8) int32func plan9Arg(inst *Inst, pc uint64, symname func(uint64) (string, uint64), arg Arg) stringfunc signumConvInt32(imm int32, width uint8) int32Generated with Arrow