Imports #
"fmt"
"strings"
"encoding/binary"
"errors"
"fmt"
"runtime"
"fmt"
"strings"
"bytes"
"fmt"
"fmt"
"strings"
"fmt"
"strings"
"encoding/binary"
"errors"
"fmt"
"runtime"
"fmt"
"strings"
"bytes"
"fmt"
"fmt"
"strings"
const AAAconst AADconst AAMconst AASconst ADCconst ADDconst ADDPDconst ADDPSconst ADDSDconst ADDSSconst ADDSUBPDconst ADDSUBPSconst AESDECconst AESDECLASTconst AESENCconst AESENCLASTconst AESIMCconst AESKEYGENASSISTconst AH8-bit
const ALconst ANDconst ANDNPDconst ANDNPSconst ANDPDconst ANDPSconst ARPL16-bit
const AXconst BHconst BLconst BLENDPDconst BLENDPSconst BLENDVPDconst BLENDVPSconst BOUNDconst BPconst BPBconst BSFconst BSRconst BSWAPconst BTconst BTCconst BTRconst BTSconst BXconst CALLconst CBWconst CDQconst CDQEconst CHconst CLconst CLCconst CLDconst CLFLUSHconst CLIconst CLTSconst CMCconst CMOVAconst CMOVAEconst CMOVBconst CMOVBEconst CMOVEconst CMOVGconst CMOVGEconst CMOVLconst CMOVLEconst CMOVNEconst CMOVNOconst CMOVNPconst CMOVNSconst CMOVOconst CMOVPconst CMOVSconst CMPconst CMPPDconst CMPPSconst CMPSBconst CMPSDconst CMPSD_XMMconst CMPSQconst CMPSSconst CMPSWconst CMPXCHGconst CMPXCHG16Bconst CMPXCHG8Bconst COMISDconst COMISSconst CPUIDconst CQOControl registers.
const CR0const CR1const CR10const CR11const CR12const CR13const CR14const CR15const CR2const CR3const CR4const CR5const CR6const CR7const CR8const CR9const CRC32const CSconst CVTDQ2PDconst CVTDQ2PSconst CVTPD2DQconst CVTPD2PIconst CVTPD2PSconst CVTPI2PDconst CVTPI2PSconst CVTPS2DQconst CVTPS2PDconst CVTPS2PIconst CVTSD2SIconst CVTSD2SSconst CVTSI2SDconst CVTSI2SSconst CVTSS2SDconst CVTSS2SIconst CVTTPD2DQconst CVTTPD2PIconst CVTTPS2DQconst CVTTPS2PIconst CVTTSD2SIconst CVTTSS2SIconst CWDconst CWDEconst CXconst DAAconst DASconst DECconst DHconst DIconst DIBconst DIVconst DIVPDconst DIVPSconst DIVSDconst DIVSSconst DLconst DPPDconst DPPSDebug registers.
const DR0const DR1const DR10const DR11const DR12const DR13const DR14const DR15const DR2const DR3const DR4const DR5const DR6const DR7const DR8const DR9const DSconst DX32-bit
const EAXconst EBPconst EBXconst ECXconst EDIconst EDXconst EIPconst EMMSconst ENTERSegment registers.
const ESconst ESIconst ESPconst EXTRACTPSThese are the errors returned by Decode.
var ErrInvalidMode = *ast.CallExprThese are the errors returned by Decode.
var ErrTruncated = *ast.CallExprThese are the errors returned by Decode.
var ErrUnrecognized = *ast.CallExpr387 floating point registers.
const F0const F1const F2const F2XM1const F3const F4const F5const F6const F7const FABSconst FADDconst FADDPconst FBLDconst FBSTPconst FCHSconst FCMOVBconst FCMOVBEconst FCMOVEconst FCMOVNBconst FCMOVNBEconst FCMOVNEconst FCMOVNUconst FCMOVUconst FCOMconst FCOMIconst FCOMIPconst FCOMPconst FCOMPPconst FCOSconst FDECSTPconst FDIVconst FDIVPconst FDIVRconst FDIVRPconst FFREEconst FFREEPconst FIADDconst FICOMconst FICOMPconst FIDIVconst FIDIVRconst FILDconst FIMULconst FINCSTPconst FISTconst FISTPconst FISTTPconst FISUBconst FISUBRconst FLDconst FLD1const FLDCWconst FLDENVconst FLDL2Econst FLDL2Tconst FLDLG2const FLDLN2const FLDPIconst FLDZconst FMULconst FMULPconst FNCLEXconst FNINITconst FNOPconst FNSAVEconst FNSTCWconst FNSTENVconst FNSTSWconst FPATANconst FPREMconst FPREM1const FPTANconst FRNDINTconst FRSTORconst FSconst FSCALEconst FSINconst FSINCOSconst FSQRTconst FSTconst FSTPconst FSUBconst FSUBPconst FSUBRconst FSUBRPconst FTSTconst FUCOMconst FUCOMIconst FUCOMIPconst FUCOMPconst FUCOMPPconst FWAITconst FXAMconst FXCHconst FXRSTORconst FXRSTOR64const FXSAVEconst FXSAVE64const FXTRACTconst FYL2Xconst FYL2XP1System registers.
const GDTRconst GSconst HADDPDconst HADDPSconst HLTconst HSUBPDconst HSUBPSconst ICEBPconst IDIVconst IDTRconst IMULconst INconst INCconst INSBconst INSDconst INSERTPSconst INSWconst INTconst INTOconst INVDconst INVLPGconst INVPCIDInstruction pointer.
const IPconst IRETconst IRETDconst IRETQconst JAconst JAEconst JBconst JBEconst JCXZconst JEconst JECXZconst JGconst JGEconst JLconst JLEconst JMPconst JNEconst JNOconst JNPconst JNSconst JOconst JPconst JRCXZconst JSconst LAHFconst LARconst LCALLconst LDDQUconst LDMXCSRconst LDSconst LDTRconst LEAconst LEAVEconst LESconst LFENCEconst LFSconst LGDTconst LGSconst LIDTconst LJMPconst LLDTconst LMSWconst LODSBconst LODSDconst LODSQconst LODSWconst LOOPconst LOOPEconst LOOPNEconst LRETconst LSLconst LSSconst LTRconst LZCNTMMX registers.
const M0const M1const M2const M3const M4const M5const M6const M7const MASKMOVDQUconst MASKMOVQconst MAXPDconst MAXPSconst MAXSDconst MAXSSconst MFENCEconst MINPDconst MINPSconst MINSDconst MINSSconst MONITORconst MOVconst MOVAPDconst MOVAPSconst MOVBEconst MOVDconst MOVDDUPconst MOVDQ2Qconst MOVDQAconst MOVDQUconst MOVHLPSconst MOVHPDconst MOVHPSconst MOVLHPSconst MOVLPDconst MOVLPSconst MOVMSKPDconst MOVMSKPSconst MOVNTDQconst MOVNTDQAconst MOVNTIconst MOVNTPDconst MOVNTPSconst MOVNTQconst MOVNTSDconst MOVNTSSconst MOVQconst MOVQ2DQconst MOVSBconst MOVSDconst MOVSD_XMMconst MOVSHDUPconst MOVSLDUPconst MOVSQconst MOVSSconst MOVSWconst MOVSXconst MOVSXDconst MOVUPDconst MOVUPSconst MOVZXconst MPSADBWconst MSWconst MULconst MULPDconst MULPSconst MULSDconst MULSSconst MWAITconst NEGconst NOPconst NOTconst ORconst ORPDconst ORPSconst OUTconst OUTSBconst OUTSDconst OUTSWconst PABSBconst PABSDconst PABSWconst PACKSSDWconst PACKSSWBconst PACKUSDWconst PACKUSWBconst PADDBconst PADDDconst PADDQconst PADDSBconst PADDSWconst PADDUSBconst PADDUSWconst PADDWconst PALIGNRconst PANDconst PANDNconst PAUSEconst PAVGBconst PAVGWconst PBLENDVBconst PBLENDWconst PCLMULQDQconst PCMPEQBconst PCMPEQDconst PCMPEQQconst PCMPEQWconst PCMPESTRIconst PCMPESTRMconst PCMPGTBconst PCMPGTDconst PCMPGTQconst PCMPGTWconst PCMPISTRIconst PCMPISTRMconst PEXTRBconst PEXTRDconst PEXTRQconst PEXTRWconst PHADDDconst PHADDSWconst PHADDWconst PHMINPOSUWconst PHSUBDconst PHSUBSWconst PHSUBWconst PINSRBconst PINSRDconst PINSRQconst PINSRWconst PMADDUBSWconst PMADDWDconst PMAXSBconst PMAXSDconst PMAXSWconst PMAXUBconst PMAXUDconst PMAXUWconst PMINSBconst PMINSDconst PMINSWconst PMINUBconst PMINUDconst PMINUWconst PMOVMSKBconst PMOVSXBDconst PMOVSXBQconst PMOVSXBWconst PMOVSXDQconst PMOVSXWDconst PMOVSXWQconst PMOVZXBDconst PMOVZXBQconst PMOVZXBWconst PMOVZXDQconst PMOVZXWDconst PMOVZXWQconst PMULDQconst PMULHRSWconst PMULHUWconst PMULHWconst PMULLDconst PMULLWconst PMULUDQconst POPconst POPAconst POPADconst POPCNTconst POPFconst POPFDconst POPFQconst PORconst PREFETCHNTAconst PREFETCHT0const PREFETCHT1const PREFETCHT2const PREFETCHWconst PSADBWconst PSHUFBconst PSHUFDconst PSHUFHWconst PSHUFLWconst PSHUFWconst PSIGNBconst PSIGNDconst PSIGNWconst PSLLDconst PSLLDQconst PSLLQconst PSLLWconst PSRADconst PSRAWconst PSRLDconst PSRLDQconst PSRLQconst PSRLWconst PSUBBconst PSUBDconst PSUBQconst PSUBSBconst PSUBSWconst PSUBUSBconst PSUBUSWconst PSUBWconst PTESTconst PUNPCKHBWconst PUNPCKHDQconst PUNPCKHQDQconst PUNPCKHWDconst PUNPCKLBWconst PUNPCKLDQconst PUNPCKLQDQconst PUNPCKLWDconst PUSHconst PUSHAconst PUSHADconst PUSHFconst PUSHFDconst PUSHFQconst PXORconst PrefixAddr16 Prefix = 0x167const PrefixAddr32 Prefix = 0x267const PrefixAddrSize Prefix = 0x67const PrefixBND Prefix = 0x2F2const PrefixCS Prefix = 0x2Econst PrefixDS Prefix = 0x3Econst PrefixData16 Prefix = 0x166const PrefixData32 Prefix = 0x266Size attributes.
const PrefixDataSize Prefix = 0x66Memory segment overrides.
const PrefixES Prefix = 0x26const PrefixFS Prefix = 0x64const PrefixGS Prefix = 0x65const PrefixIgnored Prefix = 0x4000Metadata about the role of a prefix in an instruction.
const PrefixImplicit Prefix = 0x8000const PrefixInvalid Prefix = 0x2000One of a kind.
const PrefixLOCK Prefix = 0xF0Branch prediction.
const PrefixPN Prefix = 0x12Econst PrefixPT Prefix = 0x13Econst PrefixREP Prefix = 0xF3const PrefixREPN Prefix = 0xF2The REX prefixes must be in the range [PrefixREX, PrefixREX+0x10). the other bits are set or not according to the intended use.
const PrefixREX Prefix = 0x40const PrefixREXB Prefix = 0x01const PrefixREXR Prefix = 0x04const PrefixREXW Prefix = 0x08const PrefixREXX Prefix = 0x02const PrefixSS Prefix = 0x36const PrefixVEX2Bytes Prefix = 0xC5const PrefixVEX3Bytes Prefix = 0xC4const PrefixXACQUIRE Prefix = 0x1F2const PrefixXRELEASE Prefix = 0x1F3const R10const R10Bconst R10Lconst R10Wconst R11const R11Bconst R11Lconst R11Wconst R12const R12Bconst R12Lconst R12Wconst R13const R13Bconst R13Lconst R13Wconst R14const R14Bconst R14Lconst R14Wconst R15const R15Bconst R15Lconst R15Wconst R8const R8Bconst R8Lconst R8Wconst R9const R9Bconst R9Lconst R9W64-bit
const RAXconst RBPconst RBXconst RCLconst RCPPSconst RCPSSconst RCRconst RCXconst RDFSBASEconst RDGSBASEconst RDIconst RDMSRconst RDPMCconst RDRANDconst RDTSCconst RDTSCPconst RDXconst RETconst RIPconst ROLconst RORconst ROUNDPDconst ROUNDPSconst ROUNDSDconst ROUNDSSconst RSIconst RSMconst RSPconst RSQRTPSconst RSQRTSSconst SAHFconst SARconst SBBconst SCASBconst SCASDconst SCASQconst SCASWconst SETAconst SETAEconst SETBconst SETBEconst SETEconst SETGconst SETGEconst SETLconst SETLEconst SETNEconst SETNOconst SETNPconst SETNSconst SETOconst SETPconst SETSconst SFENCEconst SGDTconst SHLconst SHLDconst SHRconst SHRDconst SHUFPDconst SHUFPSconst SIconst SIBconst SIDTconst SLDTconst SMSWconst SPconst SPBconst SQRTPDconst SQRTPSconst SQRTSDconst SQRTSSconst SSconst STCconst STDconst STIconst STMXCSRconst STOSBconst STOSDconst STOSQconst STOSWconst STRconst SUBconst SUBPDconst SUBPSconst SUBSDconst SUBSSconst SWAPGSconst SYSCALLconst SYSENTERconst SYSEXITconst SYSRETconst TASKconst TESTTask registers.
const TR0const TR1const TR2const TR3const TR4const TR5const TR6const TR7const TZCNTconst UCOMISDconst UCOMISSconst UD0const UD1const UD2const UNPCKHPDconst UNPCKHPSconst UNPCKLPDconst UNPCKLPSconst VERRconst VERWconst VMOVDQAconst VMOVDQUconst VMOVNTDQconst VMOVNTDQAconst VZEROUPPERconst WBINVDconst WRFSBASEconst WRGSBASEconst WRMSRXMM registers.
const X0const X1const X10const X11const X12const X13const X14const X15const X2const X3const X4const X5const X6const X7const X8const X9const XABORTconst XADDconst XBEGINconst XCHGconst XENDconst XGETBVconst XLATBconst XORconst XORPDconst XORPSconst XRSTORconst XRSTOR64const XRSTORSconst XRSTORS64const XSAVEconst XSAVE64const XSAVECconst XSAVEC64const XSAVEOPTconst XSAVEOPT64const XSAVESconst XSAVES64const XSETBVconst XTESTconst _ Reg = iotaconst _ Op = iotaaddr16 records the eight 16-bit addressing modes.
var addr16 = [8]Mem{...}baseReg records the base register for argument types that specify a range of registers indexed by op, regop, or rm.
var baseReg = [...]Reg{...}var cmppsOps = []string{...}var decoder = [...]uint16{...}decoderCover records coverage information for which parts of the byte code have been executed.
var decoderCover []boolvar errInternal = *ast.CallExprfixedArg records the fixed arguments corresponding to the given bytecodes.
var fixedArg = [...]Arg{...}var gccRegName = [...]string{...}var gnuOp = map[Op]string{...}var intelOp = map[Op]string{...}var intelReg = [...]string{...}isCondJmp records the conditional jumps.
var isCondJmp = [*ast.BinaryExpr]bool{...}isLoop records the loop operators.
var isLoop = [*ast.BinaryExpr]bool{...}const maxOp = XTESTmemBytes records the size of the memory pointed at by a memory argument of the given form.
var memBytes = [...]int8{...}var opNames = [...]string{...}var pclmulqOps = []string{...}var plan9Reg = [...]string{...}var plan9Suffix = [*ast.BinaryExpr]bool{...}var prefixNames = map[Prefix]string{...}const regMax = TR7var regNames = [...]string{...}Set trace to true to cause the decoder to print the PC sequence of the executed instruction codes. This is typically only useful when you are running a test of a single input case.
const trace = falseconst xArg1const xArg3const xArgALconst xArgAXconst xArgCLconst xArgCR0dashCR7const xArgCSconst xArgDR0dashDR7const xArgDSconst xArgDXconst xArgEAXconst xArgEDXconst xArgESconst xArgFSconst xArgGSconst xArgImm16const xArgImm16uconst xArgImm32const xArgImm64const xArgImm8const xArgImm8uconst xArgMconst xArgM128const xArgM1428byteconst xArgM16const xArgM16and16const xArgM16and32const xArgM16and64const xArgM16colon16const xArgM16colon32const xArgM16colon64const xArgM16intconst xArgM256const xArgM2byteconst xArgM32const xArgM32and32const xArgM32fpconst xArgM32intconst xArgM512byteconst xArgM64const xArgM64fpconst xArgM64intconst xArgM8const xArgM80bcdconst xArgM80decconst xArgM80fpconst xArgM94108byteconst xArgMemconst xArgMmconst xArgMm1const xArgMm2const xArgMm2M64const xArgMmM32const xArgMmM64const xArgMoffs16const xArgMoffs32const xArgMoffs64const xArgMoffs8const xArgPtr16colon16const xArgPtr16colon32const xArgR16const xArgR16opconst xArgR32const xArgR32M16const xArgR32M8const xArgR32opconst xArgR64const xArgR64M16const xArgR64opconst xArgR8const xArgR8opconst xArgRAXconst xArgRDXconst xArgRMconst xArgRM16const xArgRM32const xArgRM64const xArgRM8const xArgRegconst xArgRegM16const xArgRegM32const xArgRegM8const xArgRel16const xArgRel32const xArgRel8const xArgRmf16const xArgRmf32const xArgRmf64const xArgSSconst xArgSTconst xArgSTiconst xArgSregconst xArgTR0dashTR7const xArgXMM0const xArgXmmconst xArgXmm1const xArgXmm2const xArgXmm2M128const xArgXmm2M16const xArgXmm2M32const xArgXmm2M64const xArgXmmM128const xArgXmmM32const xArgXmmM64const xArgYmm1const xArgYmm2M256const xCondAddrSizeconst xCondByteconst xCondDataSizeconst xCondIs64const xCondIsMemconst xCondPrefixconst xCondSlashRconst xFail decodeOp = iotaconst xJumpconst xMatchconst xReadCbconst xReadCdconst xReadCmconst xReadCpconst xReadCwconst xReadIbconst xReadIdconst xReadIoconst xReadIwconst xReadSlashRconst xSetOpAn Args holds the instruction arguments. If an instruction has fewer than 4 arguments, the final elements in the array are nil.
type Args [4]ArgAn Imm is an integer constant.
type Imm int64An Op is an x86 opcode.
type Op uint32A Prefix represents an Intel instruction prefix. The low 8 bits are the actual prefix byte encoding, and the top 8 bits contain distinguishing bits and metadata.
type Prefix uint16Prefixes is an array of prefixes associated with a single instruction. The prefixes are listed in the same order as found in the instruction: each prefix byte corresponds to one slot in the array. The first zero in the array marks the end of the prefixes.
type Prefixes [14]PrefixA Reg is a single register. The zero Reg value has no name but indicates “no register.”
type Reg uint8A Rel is an offset relative to the current instruction pointer.
type Rel int32type SymLookup func(uint64) (string, uint64)type decodeOp uint16An Arg is a single instruction argument, one of these types: Reg, Mem, Imm, Rel.
type Arg interface {
String() string
isArg()
}An Inst is a single instruction.
type Inst struct {
Prefix Prefixes
Op Op
Opcode uint32
Args Args
Mode int
AddrSize int
DataSize int
MemBytes int
Len int
PCRel int
PCRelOff int
}A Mem is a memory reference. The general form is Segment:[Base+Scale*Index+Disp].
type Mem struct {
Segment Reg
Base Reg
Scale uint8
Index Reg
Disp int64
}Decode decodes the leading bytes in src as a single instruction. The mode arguments specifies the assumed processor mode: 16, 32, or 64 for 16-, 32-, and 64-bit execution modes.
func Decode(src []byte, mode int) (inst Inst, err error)GNUSyntax returns the GNU assembler syntax for the instruction, as defined by GNU binutils. This general form is often called “AT&T syntax” as a reference to AT&T System V Unix.
func GNUSyntax(inst Inst, pc uint64, symname SymLookup) stringGoSyntax returns the Go assembler syntax for the instruction. The syntax was originally defined by Plan 9. The pc is the program counter of the instruction, used for expanding PC-relative addresses into absolute ones. The symname function queries the symbol table for the program being disassembled. Given a target address it returns the name and base address of the symbol containing the target, if any; otherwise it returns "", 0.
func GoSyntax(inst Inst, pc uint64, symname SymLookup) stringIntelSyntax returns the Intel assembler syntax for the instruction, as defined by Intel's XED tool.
func IntelSyntax(inst Inst, pc uint64, symname SymLookup) stringIsREX reports whether p is a REX prefix byte.
func (p Prefix) IsREX() boolfunc (p Prefix) IsVEX() boolfunc (i Imm) String() stringfunc (p Prefix) String() stringfunc (i Inst) String() stringfunc (r Rel) String() stringfunc (m Mem) String() stringfunc (r Reg) String() stringfunc (op Op) String() stringfunc argBytes(inst *Inst, arg Arg) intbaseRegForBits returns the base register for a given register size in bits.
func baseRegForBits(bits int) Regfunc byteSizeSuffix(b int) stringfunc countPrefix(inst *Inst, target Prefix) intdecode1 is the implementation of Decode but takes an extra gnuCompat flag to cause it to change its behavior to mimic bugs (or at least unique features) of GNU libopcodes as used by objdump. We don't believe that logic is the right thing to do in general, but when testing against libopcodes it simplifies the comparison if we adjust a few small pieces of logic. The affected logic is in the conditional branch for "mandatory" prefixes, case xCondPrefix.
func decode1(src []byte, mode int, gnuCompat bool) (Inst, error)gnuArg returns the GNU syntax for the argument x from the instruction inst. If *usedPrefixes is false and x is a Mem, then the formatting includes any segment prefixes and sets *usedPrefixes to true.
func gnuArg(inst *Inst, pc uint64, symname SymLookup, x Arg, usedPrefixes *bool) stringinstPrefix returns an Inst describing just one prefix byte. It is only used if there is a prefix followed by an unintelligible or invalid instruction byte sequence.
func instPrefix(b byte, mode int) (Inst, error)func intelArg(inst *Inst, pc uint64, symname SymLookup, arg Arg) stringfunc (Reg) isArg()func (Rel) isArg()func (Imm) isArg()func (Mem) isArg()func isFloat(op Op) boolfunc isFloatInt(op Op) boolfunc isImm(a Arg) boolfunc isMem(a Arg) boolfunc isReg(a Arg) boolfunc isSegReg(a Arg) boolfunc isSegment(p Prefix) boolfunc markLastImplicit(inst *Inst, prefix Prefix) boolfunc memArgToSymbol(a Mem, pc uint64, instrLen int, symname SymLookup) (string, int64)func plan9Arg(inst *Inst, pc uint64, symname func(uint64) (string, uint64), arg Arg) stringprefixToSegment returns the segment register corresponding to a particular segment prefix.
func prefixToSegment(p Prefix) Regfunc regBytes(a Arg) inttruncated reports a truncated instruction. For now we use instPrefix but perhaps later we will return a specific error here.
func truncated(src []byte, mode int) (Inst, error)func unmarkImplicit(inst *Inst, prefix Prefix)Generated with Arrow