AMD64 const #
const AMD64 ArchFamilyType = iotaconst AMD64 ArchFamilyType = iotaconst ARMconst ARM64ArchFamily is the architecture family (AMD64, ARM, ...)
const ArchFamily ArchFamilyType = _ArchFamilyBigEndian reports whether the architecture is big-endian.
const BigEndian = *ast.BinaryExprDefaultPhysPageSize is the default physical page size.
const DefaultPhysPageSize = _DefaultPhysPageSizeconst GOARCH = `mips`const GOARCH = `arm64`const GOARCH = `ppc64le`const GOARCH = `armbe`const GOARCH = `sparc`const GOARCH = `s390`const GOARCH = `riscv64`const GOARCH = `amd64`const GOARCH = `mips64p32le`const GOARCH = `386`const GOARCH = `mipsle`const GOARCH = `mips64p32`const GOARCH = `riscv`const GOARCH = `s390x`const GOARCH = `arm64be`const GOARCH = `ppc`const GOARCH = `mips64le`const GOARCH = `wasm`const GOARCH = `arm`const GOARCH = `ppc64`const GOARCH = `loong64`const GOARCH = `mips64`const GOARCH = `sparc64`const I386Int64Align is the required alignment for a 64-bit integer (4 on 32-bit systems, 8 on 64-bit).
const Int64Align = PtrSizeconst Is386 = 0const Is386 = 0const Is386 = 0const Is386 = 0const Is386 = 0const Is386 = 0const Is386 = 0const Is386 = 0const Is386 = 0const Is386 = 0const Is386 = 0const Is386 = 0const Is386 = 0const Is386 = 0const Is386 = 0const Is386 = 0const Is386 = 0const Is386 = 1const Is386 = 0const Is386 = 0const Is386 = 0const Is386 = 0const Is386 = 0const IsAmd64 = 0const IsAmd64 = 0const IsAmd64 = 0const IsAmd64 = 0const IsAmd64 = 0const IsAmd64 = 1const IsAmd64 = 0const IsAmd64 = 0const IsAmd64 = 0const IsAmd64 = 0const IsAmd64 = 0const IsAmd64 = 0const IsAmd64 = 0const IsAmd64 = 0const IsAmd64 = 0const IsAmd64 = 0const IsAmd64 = 0const IsAmd64 = 0const IsAmd64 = 0const IsAmd64 = 0const IsAmd64 = 0const IsAmd64 = 0const IsAmd64 = 0const IsAmd64p32 = 0const IsAmd64p32 = 0const IsAmd64p32 = 0const IsAmd64p32 = 0const IsAmd64p32 = 0const IsAmd64p32 = 0const IsAmd64p32 = 0const IsAmd64p32 = 0const IsAmd64p32 = 0const IsAmd64p32 = 0const IsAmd64p32 = 0const IsAmd64p32 = 0const IsAmd64p32 = 0const IsAmd64p32 = 0const IsAmd64p32 = 0const IsAmd64p32 = 0const IsAmd64p32 = 0const IsAmd64p32 = 0const IsAmd64p32 = 0const IsAmd64p32 = 0const IsAmd64p32 = 0const IsAmd64p32 = 0const IsAmd64p32 = 0const IsArm = 0const IsArm = 0const IsArm = 0const IsArm = 0const IsArm = 0const IsArm = 0const IsArm = 0const IsArm = 0const IsArm = 0const IsArm = 0const IsArm = 0const IsArm = 0const IsArm = 0const IsArm = 0const IsArm = 0const IsArm = 0const IsArm = 0const IsArm = 0const IsArm = 0const IsArm = 0const IsArm = 1const IsArm = 0const IsArm = 0const IsArm64 = 0const IsArm64 = 0const IsArm64 = 0const IsArm64 = 0const IsArm64 = 0const IsArm64 = 0const IsArm64 = 1const IsArm64 = 0const IsArm64 = 0const IsArm64 = 0const IsArm64 = 0const IsArm64 = 0const IsArm64 = 0const IsArm64 = 0const IsArm64 = 0const IsArm64 = 0const IsArm64 = 0const IsArm64 = 0const IsArm64 = 0const IsArm64 = 0const IsArm64 = 0const IsArm64 = 0const IsArm64 = 0const IsArm64be = 0const IsArm64be = 0const IsArm64be = 0const IsArm64be = 0const IsArm64be = 0const IsArm64be = 0const IsArm64be = 0const IsArm64be = 1const IsArm64be = 0const IsArm64be = 0const IsArm64be = 0const IsArm64be = 0const IsArm64be = 0const IsArm64be = 0const IsArm64be = 0const IsArm64be = 0const IsArm64be = 0const IsArm64be = 0const IsArm64be = 0const IsArm64be = 0const IsArm64be = 0const IsArm64be = 0const IsArm64be = 0const IsArmbe = 0const IsArmbe = 0const IsArmbe = 0const IsArmbe = 0const IsArmbe = 0const IsArmbe = 0const IsArmbe = 0const IsArmbe = 0const IsArmbe = 0const IsArmbe = 0const IsArmbe = 0const IsArmbe = 0const IsArmbe = 0const IsArmbe = 0const IsArmbe = 0const IsArmbe = 0const IsArmbe = 0const IsArmbe = 0const IsArmbe = 1const IsArmbe = 0const IsArmbe = 0const IsArmbe = 0const IsArmbe = 0const IsLoong64 = 0const IsLoong64 = 0const IsLoong64 = 0const IsLoong64 = 0const IsLoong64 = 0const IsLoong64 = 0const IsLoong64 = 0const IsLoong64 = 0const IsLoong64 = 0const IsLoong64 = 0const IsLoong64 = 0const IsLoong64 = 0const IsLoong64 = 0const IsLoong64 = 0const IsLoong64 = 0const IsLoong64 = 1const IsLoong64 = 0const IsLoong64 = 0const IsLoong64 = 0const IsLoong64 = 0const IsLoong64 = 0const IsLoong64 = 0const IsLoong64 = 0const IsMips = 0const IsMips = 0const IsMips = 1const IsMips = 0const IsMips = 0const IsMips = 0const IsMips = 0const IsMips = 0const IsMips = 0const IsMips = 0const IsMips = 0const IsMips = 0const IsMips = 0const IsMips = 0const IsMips = 0const IsMips = 0const IsMips = 0const IsMips = 0const IsMips = 0const IsMips = 0const IsMips = 0const IsMips = 0const IsMips = 0const IsMips64 = 0const IsMips64 = 0const IsMips64 = 0const IsMips64 = 0const IsMips64 = 0const IsMips64 = 0const IsMips64 = 0const IsMips64 = 0const IsMips64 = 0const IsMips64 = 0const IsMips64 = 0const IsMips64 = 0const IsMips64 = 0const IsMips64 = 0const IsMips64 = 0const IsMips64 = 0const IsMips64 = 0const IsMips64 = 0const IsMips64 = 0const IsMips64 = 0const IsMips64 = 0const IsMips64 = 1const IsMips64 = 0const IsMips64le = 0const IsMips64le = 0const IsMips64le = 0const IsMips64le = 0const IsMips64le = 0const IsMips64le = 0const IsMips64le = 0const IsMips64le = 1const IsMips64le = 0const IsMips64le = 0const IsMips64le = 0const IsMips64le = 0const IsMips64le = 0const IsMips64le = 0const IsMips64le = 0const IsMips64le = 0const IsMips64le = 0const IsMips64le = 0const IsMips64le = 0const IsMips64le = 0const IsMips64le = 0const IsMips64le = 0const IsMips64le = 0const IsMips64p32 = 0const IsMips64p32 = 0const IsMips64p32 = 0const IsMips64p32 = 1const IsMips64p32 = 0const IsMips64p32 = 0const IsMips64p32 = 0const IsMips64p32 = 0const IsMips64p32 = 0const IsMips64p32 = 0const IsMips64p32 = 0const IsMips64p32 = 0const IsMips64p32 = 0const IsMips64p32 = 0const IsMips64p32 = 0const IsMips64p32 = 0const IsMips64p32 = 0const IsMips64p32 = 0const IsMips64p32 = 0const IsMips64p32 = 0const IsMips64p32 = 0const IsMips64p32 = 0const IsMips64p32 = 0const IsMips64p32le = 0const IsMips64p32le = 0const IsMips64p32le = 0const IsMips64p32le = 0const IsMips64p32le = 0const IsMips64p32le = 0const IsMips64p32le = 1const IsMips64p32le = 0const IsMips64p32le = 0const IsMips64p32le = 0const IsMips64p32le = 0const IsMips64p32le = 0const IsMips64p32le = 0const IsMips64p32le = 0const IsMips64p32le = 0const IsMips64p32le = 0const IsMips64p32le = 0const IsMips64p32le = 0const IsMips64p32le = 0const IsMips64p32le = 0const IsMips64p32le = 0const IsMips64p32le = 0const IsMips64p32le = 0const IsMipsle = 0const IsMipsle = 0const IsMipsle = 0const IsMipsle = 0const IsMipsle = 0const IsMipsle = 0const IsMipsle = 0const IsMipsle = 0const IsMipsle = 0const IsMipsle = 0const IsMipsle = 0const IsMipsle = 1const IsMipsle = 0const IsMipsle = 0const IsMipsle = 0const IsMipsle = 0const IsMipsle = 0const IsMipsle = 0const IsMipsle = 0const IsMipsle = 0const IsMipsle = 0const IsMipsle = 0const IsMipsle = 0const IsPpc = 0const IsPpc = 0const IsPpc = 0const IsPpc = 0const IsPpc = 0const IsPpc = 0const IsPpc = 0const IsPpc = 0const IsPpc = 0const IsPpc = 0const IsPpc = 0const IsPpc = 0const IsPpc = 0const IsPpc = 1const IsPpc = 0const IsPpc = 0const IsPpc = 0const IsPpc = 0const IsPpc = 0const IsPpc = 0const IsPpc = 0const IsPpc = 0const IsPpc = 0const IsPpc64 = 0const IsPpc64 = 0const IsPpc64 = 0const IsPpc64 = 0const IsPpc64 = 0const IsPpc64 = 0const IsPpc64 = 0const IsPpc64 = 0const IsPpc64 = 0const IsPpc64 = 0const IsPpc64 = 0const IsPpc64 = 0const IsPpc64 = 0const IsPpc64 = 0const IsPpc64 = 0const IsPpc64 = 0const IsPpc64 = 0const IsPpc64 = 0const IsPpc64 = 0const IsPpc64 = 0const IsPpc64 = 0const IsPpc64 = 0const IsPpc64 = 1const IsPpc64le = 0const IsPpc64le = 0const IsPpc64le = 0const IsPpc64le = 0const IsPpc64le = 0const IsPpc64le = 0const IsPpc64le = 0const IsPpc64le = 0const IsPpc64le = 0const IsPpc64le = 0const IsPpc64le = 0const IsPpc64le = 0const IsPpc64le = 0const IsPpc64le = 0const IsPpc64le = 0const IsPpc64le = 0const IsPpc64le = 0const IsPpc64le = 0const IsPpc64le = 0const IsPpc64le = 0const IsPpc64le = 1const IsPpc64le = 0const IsPpc64le = 0const IsRiscv = 0const IsRiscv = 0const IsRiscv = 0const IsRiscv = 0const IsRiscv = 0const IsRiscv = 0const IsRiscv = 0const IsRiscv = 0const IsRiscv = 0const IsRiscv = 0const IsRiscv = 0const IsRiscv = 0const IsRiscv = 0const IsRiscv = 0const IsRiscv = 0const IsRiscv = 0const IsRiscv = 1const IsRiscv = 0const IsRiscv = 0const IsRiscv = 0const IsRiscv = 0const IsRiscv = 0const IsRiscv = 0const IsRiscv64 = 0const IsRiscv64 = 0const IsRiscv64 = 0const IsRiscv64 = 0const IsRiscv64 = 0const IsRiscv64 = 0const IsRiscv64 = 0const IsRiscv64 = 0const IsRiscv64 = 1const IsRiscv64 = 0const IsRiscv64 = 0const IsRiscv64 = 0const IsRiscv64 = 0const IsRiscv64 = 0const IsRiscv64 = 0const IsRiscv64 = 0const IsRiscv64 = 0const IsRiscv64 = 0const IsRiscv64 = 0const IsRiscv64 = 0const IsRiscv64 = 0const IsRiscv64 = 0const IsRiscv64 = 0const IsS390 = 0const IsS390 = 0const IsS390 = 0const IsS390 = 1const IsS390 = 0const IsS390 = 0const IsS390 = 0const IsS390 = 0const IsS390 = 0const IsS390 = 0const IsS390 = 0const IsS390 = 0const IsS390 = 0const IsS390 = 0const IsS390 = 0const IsS390 = 0const IsS390 = 0const IsS390 = 0const IsS390 = 0const IsS390 = 0const IsS390 = 0const IsS390 = 0const IsS390 = 0const IsS390x = 0const IsS390x = 0const IsS390x = 0const IsS390x = 0const IsS390x = 0const IsS390x = 0const IsS390x = 0const IsS390x = 0const IsS390x = 0const IsS390x = 0const IsS390x = 0const IsS390x = 0const IsS390x = 0const IsS390x = 0const IsS390x = 0const IsS390x = 0const IsS390x = 1const IsS390x = 0const IsS390x = 0const IsS390x = 0const IsS390x = 0const IsS390x = 0const IsS390x = 0const IsSparc = 0const IsSparc = 1const IsSparc = 0const IsSparc = 0const IsSparc = 0const IsSparc = 0const IsSparc = 0const IsSparc = 0const IsSparc = 0const IsSparc = 0const IsSparc = 0const IsSparc = 0const IsSparc = 0const IsSparc = 0const IsSparc = 0const IsSparc = 0const IsSparc = 0const IsSparc = 0const IsSparc = 0const IsSparc = 0const IsSparc = 0const IsSparc = 0const IsSparc = 0const IsSparc64 = 0const IsSparc64 = 0const IsSparc64 = 0const IsSparc64 = 0const IsSparc64 = 0const IsSparc64 = 0const IsSparc64 = 0const IsSparc64 = 0const IsSparc64 = 0const IsSparc64 = 0const IsSparc64 = 0const IsSparc64 = 0const IsSparc64 = 0const IsSparc64 = 0const IsSparc64 = 0const IsSparc64 = 0const IsSparc64 = 0const IsSparc64 = 1const IsSparc64 = 0const IsSparc64 = 0const IsSparc64 = 0const IsSparc64 = 0const IsSparc64 = 0const IsWasm = 0const IsWasm = 0const IsWasm = 0const IsWasm = 0const IsWasm = 0const IsWasm = 0const IsWasm = 0const IsWasm = 0const IsWasm = 0const IsWasm = 0const IsWasm = 0const IsWasm = 0const IsWasm = 0const IsWasm = 0const IsWasm = 1const IsWasm = 0const IsWasm = 0const IsWasm = 0const IsWasm = 0const IsWasm = 0const IsWasm = 0const IsWasm = 0const IsWasm = 0const LOONG64const MIPSconst MIPS64MinFrameSize is the size of the system-reserved words at the bottom of a frame (just above the architectural stack pointer). It is zero on x86 and PtrSize on most non-x86 (LR-based) systems. On PowerPC it is larger, to cover three more reserved words: the compiler word, the link editor word, and the TOC save word.
const MinFrameSize = _MinFrameSizePCQuantum is the minimal unit for a program counter (1 on x86, 4 on most other systems). The various PC tables record PC deltas pre-divided by PCQuantum.
const PCQuantum = _PCQuantumconst PPC64PtrSize is the size of a pointer in bytes - unsafe.Sizeof(uintptr(0)) but as an ideal constant. It is also the size of the machine's native word size (that is, 4 on 32-bit systems, 8 on 64-bit).
const PtrSize = *ast.BinaryExprconst RISCV64const S390XStackAlign is the required alignment of the SP register. The stack must be at least word aligned, but some architectures require more.
const StackAlign = _StackAlignconst WASMconst _ArchFamily = WASMconst _ArchFamily = AMD64const _ArchFamily = LOONG64const _ArchFamily = S390Xconst _ArchFamily = MIPSconst _ArchFamily = MIPS64const _ArchFamily = PPC64const _ArchFamily = MIPSconst _ArchFamily = PPC64const _ArchFamily = ARMconst _ArchFamily = I386const _ArchFamily = MIPS64const _ArchFamily = RISCV64const _ArchFamily = ARM64const _DefaultPhysPageSize = 65536const _DefaultPhysPageSize = 65536const _DefaultPhysPageSize = 4096const _DefaultPhysPageSize = 4096const _DefaultPhysPageSize = 65536const _DefaultPhysPageSize = 65536const _DefaultPhysPageSize = 16384const _DefaultPhysPageSize = 65536const _DefaultPhysPageSize = 65536const _DefaultPhysPageSize = 65536const _DefaultPhysPageSize = 4096const _DefaultPhysPageSize = 16384const _DefaultPhysPageSize = 4096const _DefaultPhysPageSize = 16384const _MinFrameSize = 8const _MinFrameSize = 8const _MinFrameSize = 4const _MinFrameSize = 8const _MinFrameSize = 0const _MinFrameSize = 32const _MinFrameSize = 8const _MinFrameSize = 0const _MinFrameSize = 4const _MinFrameSize = 32const _MinFrameSize = 8const _MinFrameSize = 0const _MinFrameSize = 4const _MinFrameSize = 8const _PCQuantum = 4const _PCQuantum = 4const _PCQuantum = 2const _PCQuantum = 4const _PCQuantum = 4const _PCQuantum = 4const _PCQuantum = 1const _PCQuantum = 4const _PCQuantum = 4const _PCQuantum = 1const _PCQuantum = 4const _PCQuantum = 4const _PCQuantum = 1const _PCQuantum = 4const _StackAlign = 16const _StackAlign = PtrSizeconst _StackAlign = 16const _StackAlign = PtrSizeconst _StackAlign = PtrSizeconst _StackAlign = PtrSizeconst _StackAlign = PtrSizeconst _StackAlign = PtrSizeconst _StackAlign = PtrSizeconst _StackAlign = 16const _StackAlign = PtrSizeconst _StackAlign = PtrSizeconst _StackAlign = PtrSizeconst _StackAlign = PtrSizetype ArchFamilyType intGenerated with Arrow